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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:21:36 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-20 12:21:36 -0700 |
| commit | 3fb839e2555755d29cb8304af9a9cc10d1f5e5ef (patch) | |
| tree | 81978ed22a9511e259c7c37ffc80e061b2846d84 /passes | |
| parent | eb597431f03cb402db4fc8a514c031efc29e6580 (diff) | |
| parent | f3781f98db227f160e08b2fc7cf8c61f663a56c9 (diff) | |
| download | yosys-3fb839e2555755d29cb8304af9a9cc10d1f5e5ef.tar.gz yosys-3fb839e2555755d29cb8304af9a9cc10d1f5e5ef.tar.bz2 yosys-3fb839e2555755d29cb8304af9a9cc10d1f5e5ef.zip | |
Merge remote-tracking branch 'origin/master' into xc7dsp
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/cmds/add.cc | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index af6f7043d..dd05ac81f 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -105,6 +105,11 @@ struct AddPass : public Pass { log("Like 'add -input', but also connect the signal between instances of the\n"); log("selected modules.\n"); log("\n"); + log("\n"); + log(" add -mod <name[s]>\n"); + log("\n"); + log("Add module[s] with the specified name[s].\n"); + log("\n"); } void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE { @@ -113,6 +118,7 @@ struct AddPass : public Pass { bool arg_flag_input = false; bool arg_flag_output = false; bool arg_flag_global = false; + bool mod_mode = false; int arg_width = 0; size_t argidx; @@ -133,8 +139,20 @@ struct AddPass : public Pass { arg_width = atoi(args[++argidx].c_str()); continue; } + if (arg == "-mod") { + mod_mode = true; + argidx++; + break; + } break; } + + if (mod_mode) { + for (; argidx < args.size(); argidx++) + design->addModule(RTLIL::escape_id(args[argidx])); + return; + } + extra_args(args, argidx, design); for (auto &mod : design->modules_) |