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authorEddie Hung <eddie@fpgeh.com>2019-09-26 14:31:02 -0700
committerEddie Hung <eddie@fpgeh.com>2019-09-26 14:31:02 -0700
commit26657037b8de3cf09bafb2bca3940515dad96222 (patch)
tree19d210112815d097852579691d0840ceb8a0c588 /passes
parent5b9deef10df2ab958112f6ff55f27776e492f187 (diff)
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Update doc with max cascade chain of 20
Diffstat (limited to 'passes')
-rw-r--r--passes/pmgen/xilinx_dsp.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 6ce5f2e16..11c7e5ea8 100644
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -576,8 +576,10 @@ struct XilinxDspPass : public Pass {
log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
log("input to the post-adder -- a pattern common for summing partial products to\n");
- log("implement wide multipliers). Initial support also exists for similar cascading\n");
- log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n");
+ log("implement wide multipliers). Limited support also exists for similar cascading\n");
+ log("for A and B using '[AB]COUT' -> '[AB]CIN'. Currently, cascade chains are limited\n");
+ log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n");
+ log("device.\n");
log("\n");
log("\n");
log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");