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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 17:22:30 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 17:22:30 -0700 |
| commit | aeb15398182abf5de7e340976e204195ab80a739 (patch) | |
| tree | 3ae1eea19b1b7820c54f9b5413711913a0ad42cf /passes | |
| parent | 63940913d21fcfb18cd844d7e5b9c8b41a82295b (diff) | |
| download | yosys-aeb15398182abf5de7e340976e204195ab80a739.tar.gz yosys-aeb15398182abf5de7e340976e204195ab80a739.tar.bz2 yosys-aeb15398182abf5de7e340976e204195ab80a739.zip | |
Rework xilinx_dsp postAdd for new wreduce call
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.pmg | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/passes/pmgen/xilinx_dsp.pmg b/passes/pmgen/xilinx_dsp.pmg index bca44c08d..e256f7d7e 100644 --- a/passes/pmgen/xilinx_dsp.pmg +++ b/passes/pmgen/xilinx_dsp.pmg @@ -271,9 +271,9 @@ match postAdd filter !ffMcemux || nusers(port(postAdd, AB)) == 3 index <SigBit> port(postAdd, AB)[0] === sigP[0] - filter GetSize(port(postAdd, AB)) <= GetSize(sigP) - filter port(postAdd, AB) == sigP.extract(0, GetSize(port(postAdd, AB))) - filter nusers(sigP.extract_end(GetSize(port(postAdd, AB)))) <= 1 + filter GetSize(port(postAdd, AB)) >= GetSize(sigP) + filter port(postAdd, AB).extract(0, GetSize(sigP)) == sigP + filter port(postAdd, AB).extract_end(GetSize(sigP)) == SigSpec(sigP[GetSize(sigP)-1], GetSize(port(postAdd, AB))-GetSize(sigP)) set postAddAB AB optional endmatch |