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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 11:57:53 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-27 11:57:53 -0700 |
| commit | aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee (patch) | |
| tree | 675f010f9a3ebb080eafb8bc5c6845908f52bcb8 /passes | |
| parent | 26657037b8de3cf09bafb2bca3940515dad96222 (diff) | |
| download | yosys-aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee.tar.gz yosys-aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee.tar.bz2 yosys-aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee.zip | |
Ooops AREG and BREG to default to -1
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp_cascade.pmg | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg index 714316808..6f4ac5849 100644 --- a/passes/pmgen/xilinx_dsp_cascade.pmg +++ b/passes/pmgen/xilinx_dsp_cascade.pmg @@ -146,7 +146,7 @@ code next endcode code argQ clock AREG - AREG = 0; + AREG = -1; if (next) { Cell *prev = std::get<0>(chain.back()); if (param(prev, \AREG, 2).as_int() > 0 && @@ -175,7 +175,7 @@ reject_AREG: ; endcode code argQ clock BREG - BREG = 0; + BREG = -1; if (next) { Cell *prev = std::get<0>(chain.back()); if (param(prev, \BREG, 2).as_int() > 0 && |