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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 10:31:55 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-26 10:31:55 -0700 |
| commit | c0bb1d22e81b935e90032ed886e58787b3e61df5 (patch) | |
| tree | 73a83434f99b7efc0be45ae76afa01a984dda447 /passes | |
| parent | 781dda6175c86fcb2b08d055565d3d99a687e636 (diff) | |
| download | yosys-c0bb1d22e81b935e90032ed886e58787b3e61df5.tar.gz yosys-c0bb1d22e81b935e90032ed886e58787b3e61df5.tar.bz2 yosys-c0bb1d22e81b935e90032ed886e58787b3e61df5.zip | |
Remove newline
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/xilinx_dsp.cc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc index db8fba38b..4c297a50a 100644 --- a/passes/pmgen/xilinx_dsp.cc +++ b/passes/pmgen/xilinx_dsp.cc @@ -494,7 +494,6 @@ void xilinx_dsp_packC(xilinx_dsp_CREG_pm &pm) log_debug("Analysing %s.%s for Xilinx DSP packing (CREG).\n", log_id(pm.module), log_id(st.dsp)); log_debug("ffC: %s %s %s\n", log_id(st.ffC, "--"), log_id(st.ffCcemux, "--"), log_id(st.ffCrstmux, "--")); - log_debug("\n"); Cell *cell = st.dsp; |