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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 14:05:59 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-25 14:05:59 -0700 |
| commit | 486dd7c483d4277ffb09975fb943881bdc122f4d (patch) | |
| tree | 4f46ad1ce11a1914ad04766c940bc8de77a888ff /passes | |
| parent | 53ea5daa42db335a69d3fccbf237fe5555f4bccb (diff) | |
| download | yosys-486dd7c483d4277ffb09975fb943881bdc122f4d.tar.gz yosys-486dd7c483d4277ffb09975fb943881bdc122f4d.tar.bz2 yosys-486dd7c483d4277ffb09975fb943881bdc122f4d.zip | |
unextend only used in init
Diffstat (limited to 'passes')
| -rw-r--r-- | passes/pmgen/ice40_dsp.pmg | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/passes/pmgen/ice40_dsp.pmg b/passes/pmgen/ice40_dsp.pmg index 046aae9e2..9330dd09b 100644 --- a/passes/pmgen/ice40_dsp.pmg +++ b/passes/pmgen/ice40_dsp.pmg @@ -1,6 +1,5 @@ pattern ice40_dsp -udata <std::function<SigSpec(const SigSpec&)>> unextend state <SigBit> clock state <bool> clock_pol cd_signed o_lo state <SigSpec> sigA sigB sigCD sigH sigO @@ -28,7 +27,7 @@ match mul endmatch code sigA sigB sigH - unextend = [](const SigSpec &sig) { + auto unextend = [](const SigSpec &sig) { int i; for (i = GetSize(sig)-1; i > 0; i--) if (sig[i] != sig[i-1]) |