iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Merge pull request #1412 from YosysHQ/eddie/equiv_opt_async2sync	Clifford Wolf	2019-09-30	1	-0/+2
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\| *	equiv_opt to call async2sync when not -multiclock like SymbiYosys	Eddie Hung	2019-09-27	1	-0/+2
* \|	Fix $dlatch handling in async2sync	Clifford Wolf	2019-09-30	1	-0/+1
* \|	Merge pull request #1359 from YosysHQ/xc7dsp	Eddie Hung	2019-09-29	12	-229/+2498
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\| *	Ooops AREG and BREG to default to -1	Eddie Hung	2019-09-27	1	-2/+2
\| *	Update doc with max cascade chain of 20	Eddie Hung	2019-09-26	1	-2/+4
\| *	Do not always zero out C (e.g. during cascade breaks)	Eddie Hung	2019-09-26	2	-7/+3
\| *	Update doc	Eddie Hung	2019-09-26	1	-1/+2
\| *	Zero out ports	Eddie Hung	2019-09-26	1	-2/+2
\| *	xilinx_dsp_cascade to also cascade AREG and BREG	Eddie Hung	2019-09-26	2	-454/+172
\| *	Try recursive pmgen for P cascade	Eddie Hung	2019-09-26	1	-88/+118
\| *	CREG to check for \keep	Eddie Hung	2019-09-26	1	-0/+3
\| *	Remove newline	Eddie Hung	2019-09-26	1	-1/+0
\| *	Do not die if DSP48E1.P has no users (would otherwise get 'clean'-ed)	Eddie Hung	2019-09-25	1	-1/+5
\| *	Reject if (* init *) present	Eddie Hung	2019-09-25	2	-0/+6
\| *	Rework xilinx_dsp postAdd for new wreduce call	Eddie Hung	2019-09-25	1	-3/+3
\| *	Fix memory issue since SigSpec& could be invalidated	Eddie Hung	2019-09-25	1	-6/+10
\| *	unextend only used in init	Eddie Hung	2019-09-25	1	-2/+1
\| *	Call 'wreduce' after mul2dsp to avoid unextend()	Eddie Hung	2019-09-25	1	-5/+4
\| *	"abc_padding" attr for blackbox outputs that were padded, remove them later	Eddie Hung	2019-09-23	1	-3/+16
\| *	Set [AB]CASCREG to legal values	Eddie Hung	2019-09-23	1	-6/+10
\| *	Comment to explain separating CREG packing	Eddie Hung	2019-09-23	1	-0/+8
\| *	Separate out CREG packing into new pattern, to avoid conflict with PREG	Eddie Hung	2019-09-23	4	-46/+273
\| *	Move log_debug("\n") later	Eddie Hung	2019-09-23	1	-1/+1
\| *	Move unextend initialisation later	Eddie Hung	2019-09-23	1	-12/+9
\| *	Use new port() overload once more	Eddie Hung	2019-09-23	1	-2/+2
\| *	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-23	1	-1/+7
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\| * \|	Use new port/param overload in pmg	Eddie Hung	2019-09-20	4	-22/+22
\| * \|	Output pattern matcher items as log_debug()	Eddie Hung	2019-09-20	2	-31/+27
\| * \|	OPMODE is port not param	Eddie Hung	2019-09-20	1	-7/+6
\| * \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-20	1	-0/+18
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\| * \| \|	Do not run xilinx_dsp_cascadeAB for now	Eddie Hung	2019-09-20	1	-1/+2
\| * \| \|	WIP for xiinx_dsp_cascadeAB	Eddie Hung	2019-09-20	1	-3/+499
\| * \| \|	Run until convergence	Eddie Hung	2019-09-20	1	-3/+9
\| * \| \|	Cleanup ice40_dsp.pmg	Eddie Hung	2019-09-20	1	-12/+6
\| * \| \|	Cleanup xilinx_dsp	Eddie Hung	2019-09-20	1	-1/+1
\| * \| \|	More exceptions	Eddie Hung	2019-09-20	1	-2/+2
\| * \| \|	Update doc	Eddie Hung	2019-09-20	1	-2/+2
\| * \| \|	Add a xilinx_dsp_cascade matcher for PCIN -> PCOUT	Eddie Hung	2019-09-20	4	-54/+105
\| * \| \|	Add an overload for port/param with default value	Eddie Hung	2019-09-20	1	-0/+8
\| * \| \|	Small cleanup	Eddie Hung	2019-09-20	1	-19/+18
\| * \| \|	Disable support for SB_MAC16 reset since it is async	Eddie Hung	2019-09-19	2	-3/+7
\| * \| \|	SB_MAC16 ffCD to not pack same as ffO	Eddie Hung	2019-09-19	1	-2/+2
\| * \| \|	Clarify	Eddie Hung	2019-09-19	1	-1/+2
\| * \| \|	Update doc for ice40_dsp	Eddie Hung	2019-09-19	1	-1/+10
\| * \| \|	Add an index	Eddie Hung	2019-09-19	2	-0/+3
\| * \| \|	Fix width of D	Eddie Hung	2019-09-19	1	-1/+1
\| * \| \|	Use ID() macro	Eddie Hung	2019-09-19	2	-210/+210
\| * \| \|	Merge remote-tracking branch 'origin/clifford/fix1381' into xc7dsp	Eddie Hung	2019-09-19	3	-5/+173
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\| * \| \| \|	Re-enable sign extension for C input	Eddie Hung	2019-09-19	1	-4/+4