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* techmap: use C++11 default member initializers. NFC.whitequark2020-06-021-16/+6
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* techmap: simplify.whitequark2020-06-021-7/+1
| | | | `rewrite_filename` is already called in `Frontend::extra_args`.
* techmap: use +/techmap.v instead of an ad-hoc code generator.whitequark2020-06-021-3/+1
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* techmap: Replace naughty `const_cast<>()`s.Alberto Gonzalez2020-05-141-2/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: Replace pseudo-private member usage with the range accessor ↵Alberto Gonzalez2020-05-141-3/+3
| | | | function and some naughty `const_cast<>()`s.
* techmap: sort celltypeMap as it determines techmap orderEddie Hung2020-05-141-1/+5
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* Replace `std::set`s using custom comparators with `pool`.Alberto Gonzalez2020-05-141-4/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* techmap: prefix special wires with backslash for use as IdStringEddie Hung2020-05-141-11/+12
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* Further clean up `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-5/+6
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Use `emplace()` for more efficient insertion into various `dict`s.Alberto Gonzalez2020-05-141-8/+8
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* Build constant bits directly rather than constructing an object and copying ↵Alberto Gonzalez2020-05-141-2/+5
| | | | its bits.
* Replace `std::set` with `pool` for `cell_to_inbit` and `outbit_to_cell`.Alberto Gonzalez2020-05-141-2/+2
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* Use `emplace()` rather than `insert()`.Alberto Gonzalez2020-05-141-1/+1
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* Clean up pseudo-private member usage and ensure range iteration uses ↵Alberto Gonzalez2020-05-141-17/+17
| | | | references where possible to avoid unnecessary copies.
* Clean up extraneous buffer.Alberto Gonzalez2020-05-141-5/+2
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* Replace `std::map` with `dict` for `unique_bit_id`.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `port_new2old_map`, `port_connmap`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `cellbits_to_tplbits`.
* Replace `std::map` with `dict` for `connbits_map`, `cell_to_inbit`, and ↵Alberto Gonzalez2020-05-141-3/+3
| | | | `outbit_to_cell`.
* Replace `std::map` with `dict` for `TechmapWires` type.Alberto Gonzalez2020-05-141-1/+1
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* Replace `std::map` with `dict` for `celltypeMap`.Alberto Gonzalez2020-05-141-3/+3
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* Replace `std::set` with `pool` for `handled_cells` and `techmap_wire_names`.Alberto Gonzalez2020-05-141-4/+4
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* Replace `std::map` with `dict` for `positional_ports`.Alberto Gonzalez2020-05-141-1/+1
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* Add specialized `hash()` for type `dict` and use a `dict` instead of a ↵Alberto Gonzalez2020-05-141-4/+4
| | | | `std::map` for `techmap_cache` and `techmap_do_cache`.
* Replace `std::map` with `dict` for `simplemap_mappers`.Alberto Gonzalez2020-05-141-1/+1
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* Use `nullptr` instead of `NULL` in `passes/techmap/techmap.cc`.Alberto Gonzalez2020-05-141-10/+10
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* Replace `std::string` and `RTLIL::IdString` with `IdString` in ↵Alberto Gonzalez2020-05-141-21/+21
| | | | | | `passes/techmap/techmap.cc`. Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Do not modify design modules while iterating over `modules()`.Alberto Gonzalez2020-05-141-1/+4
| | | | Co-Authored-By: Eddie Hung <eddie@fpgeh.com>
* Clean up pseudo-private member usage, superfluous `std::vector` ↵Alberto Gonzalez2020-05-141-76/+70
| | | | instantiation, and `RTLIL::id2cstr()` usage in `passes/techmap/techmap.cc`.
* techmap: fix error messageEddie Hung2020-04-141-1/+1
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* kernel: big fat patch to use more ID::*, otherwise ID(*)Eddie Hung2020-04-021-40/+40
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* Merge pull request #1845 from YosysHQ/eddie/kernel_speedupEddie Hung2020-04-021-2/+2
|\ | | | | kernel: speedup by using more pass-by-const-ref
| * kernel: SigSpec use more const& + overloads to prevent implicit SigSpecEddie Hung2020-03-131-2/+2
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* | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-1/+1
|/ | | | Fixes #1804.
* Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolfEddie Hung2019-10-021-4/+8
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* techmap wires named _TECHMAP_REPLACE_.<identifier> to create aliasEddie Hung2019-09-301-0/+10
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* Fix _TECHMAP_REMOVEINIT_ handling.Marcin Kościelnicki2019-09-271-13/+17
| | | | | | | | Previously, this wire was handled in the code that populated the "do or do not" techmap cache, resulting in init value removal being performed only for the first use of a given template. Fixes the problem identified in #1396.
* Trim mismatched connection to be same (smallest) sizeEddie Hung2019-09-201-0/+6
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* Fix first testcase in #1391Eddie Hung2019-09-201-1/+1
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* Add techmap_autopurge attribute, fixes #1381Clifford Wolf2019-09-191-5/+49
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* techmap: Add support for extracting init values of portsMarcin Kościelnicki2019-09-071-1/+70
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* Rename conflicting wires on flatten/techmap, add "hierconn" attribute, fixes ↵Clifford Wolf2019-09-051-8/+24
| | | | | | #1220 Signed-off-by: Clifford Wolf <clifford@clifford.at>
* Add flatten handling of pre-existing wires as created by interfaces, fixes #1145Clifford Wolf2019-09-051-8/+20
| | | | Signed-off-by: Clifford Wolf <clifford@clifford.at>
* GrammarEddie Hung2019-08-201-1/+1
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* techmap -max_iter to apply to each module individuallyEddie Hung2019-08-201-4/+6
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* Use ID::keep more liberally tooEddie Hung2019-08-151-1/+1
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* Use more ID::{A,B,Y,blackbox,whitebox}Eddie Hung2019-08-151-1/+1
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* ID(\\.*) -> ID(.*)Eddie Hung2019-08-151-32/+32
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* Transform all "\\*" identifiers into ID()Eddie Hung2019-08-151-48/+48
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* Transform "$.*" to ID("$.*") in passes/techmapEddie Hung2019-08-151-4/+4
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* More use of IdString::in()Eddie Hung2019-08-151-2/+2
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