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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-15 14:50:10 -0700 |
| commit | 52355f5185fe42e28775e897f458b38a439c0ec5 (patch) | |
| tree | 83d8984e70806c9bcc8cd6d72ea81456ca76aba6 /passes/techmap/techmap.cc | |
| parent | 6cd8cace0c1d2a9f7b1f1cd56a223c38a5ea799a (diff) | |
| download | yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.gz yosys-52355f5185fe42e28775e897f458b38a439c0ec5.tar.bz2 yosys-52355f5185fe42e28775e897f458b38a439c0ec5.zip | |
Use more ID::{A,B,Y,blackbox,whitebox}
Diffstat (limited to 'passes/techmap/techmap.cc')
| -rw-r--r-- | passes/techmap/techmap.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index e81dc33ee..fa038c1b9 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -520,7 +520,7 @@ struct TechmapWorker int port_counter = 1; for (auto &c : extmapper_cell->connections_) { RTLIL::Wire *w = extmapper_module->addWire(c.first, GetSize(c.second)); - if (w->name.in(ID(Y), ID(Q))) + if (w->name.in(ID::Y, ID(Q))) w->port_output = true; else w->port_input = true; |