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* Merge pull request #905 from christian-krieg/feature/python_bindingsClifford Wolf2019-04-221-1/+26
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| * Merge remote-tracking branch 'origin/master' into feature/python_bindingsBenedikt Tutzer2019-03-281-6/+74
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| * | Deleted duplicate DestructorBenedikt Tutzer2018-08-211-1/+0
| * | added some checks if python is enabled to make sure everything compiles if py...Benedikt Tutzer2018-08-201-0/+1
| * | Added Wrappers for:Benedikt Tutzer2018-08-131-3/+11
| * | added destructors for wires and cellsBenedikt Tutzer2018-07-101-1/+2
| * | multiple designs can now exist independent from each other. Cells/Wires/Modul...Benedikt Tutzer2018-07-091-0/+16
* | | Add "wbflip" commandClifford Wolf2019-04-201-1/+1
* | | Ignore 'whitebox' attr in flatten with "-wb" optionEddie Hung2019-04-181-2/+2
* | | Add "whitebox" attribute, add "read_verilog -wb"Clifford Wolf2019-04-181-0/+4
* | | Add "read_ilang -lib"Clifford Wolf2019-04-051-0/+1
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* | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signalsClifford Wolf2019-03-231-0/+8
* | Improve determinism of IdString DB for similar scriptsClifford Wolf2019-03-111-5/+59
* | proc_clean: remove any empty cases if all cases use all-def compare.whitequark2018-12-231-0/+4
* | Support for 'modports' for System Verilog interfacesRuben Undheim2018-10-121-1/+1
* | Synthesis support for SystemVerilog interfacesRuben Undheim2018-10-121-0/+2
* | Consistent use of 'override' for virtual methods in derived classes.Henner Zeller2018-07-201-1/+1
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* Add $allconst and $allseq cell typesClifford Wolf2018-02-231-0/+2
* Bugfix in hierarchy handling of blackbox module portsClifford Wolf2018-01-051-1/+1
* Add RTLIL::Const::is_fully_ones()Clifford Wolf2017-12-141-0/+1
* Add SigSpec::is_fully_ones()Clifford Wolf2017-12-141-0/+1
* Add src arguments to all cell creator helper functionsClifford Wolf2017-09-091-153/+153
* Merge remote-tracking branch 'upstream/master'Jason Lowdermilk2017-08-301-0/+4
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| * Add {get,set}_src_attribute() methods on RTLIL::AttrObjectClifford Wolf2017-08-301-0/+4
* | Add support for source line tracking through synthesis phaseJason Lowdermilk2017-08-291-18/+18
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* Add Const methods is_fully_zero(), is_fully_def(), and is_fully_undef()Clifford Wolf2017-08-181-0/+4
* Add "setundef -anyseq"Clifford Wolf2017-05-281-12/+12
* Add missing AndnotGate() and OrnotGate() declarations to rtlil.hClifford Wolf2017-05-171-13/+15
* Add $_ANDNOT_ and $_ORNOT_ gatesClifford Wolf2017-05-171-13/+15
* Add $live and $fair cell types, add support for s_eventually keywordClifford Wolf2017-02-251-0/+2
* Add $cover cell type and SVA cover() supportClifford Wolf2017-02-041-0/+1
* Remember global declarations and defines accross read_verilog callsClifford Wolf2016-11-151-1/+2
* Added $anyseq cell typeClifford Wolf2016-10-141-0/+1
* Added $global_clock verilog syntax support for creating $ff cellsClifford Wolf2016-10-141-1/+2
* Added $ff and $_FF_ cell typesClifford Wolf2016-10-121-0/+2
* Improvements in assertpmuxClifford Wolf2016-09-071-0/+3
* Removed $predict againClifford Wolf2016-08-281-1/+0
* Added basic support for $expect cellsClifford Wolf2016-07-131-0/+2
* A few modifications after pull request commentsRuben Undheim2016-06-181-2/+1
* Added support for SystemVerilog packages with localparam definitionsRuben Undheim2016-06-181-0/+2
* Added addBufGate module methodClifford Wolf2016-02-021-0/+2
* Meaningless coding style changeClifford Wolf2016-01-311-1/+0
* rtlil: duplicate remove2() for std::set<>Rick Altherr2016-01-291-0/+2
* rtlil: change IdString comparison operators to take references instead of copiesRick Altherr2016-01-291-3/+3
* Removed dangling ';' in rtlil.hClifford Wolf2015-11-261-2/+2
* renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()Clifford Wolf2015-10-241-1/+2
* Cosmetic fix in Module::addLut()Clifford Wolf2015-09-181-1/+1
* Added $tribuf and $_TBUF_ cell typesClifford Wolf2015-08-161-0/+1
* Spell check (by Larry Doolittle)Clifford Wolf2015-08-141-1/+1
* Fixed trailing whitespacesClifford Wolf2015-07-021-11/+11
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