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| author | Clifford Wolf <clifford@clifford.at> | 2019-04-05 17:31:49 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-04-05 17:31:49 +0200 |
| commit | dfb242c905ff10bb4038f080aeb74a820e8fbd00 (patch) | |
| tree | 7a900803745f7ab020ad801bfa4b4b8c1f2877c7 /kernel/rtlil.h | |
| parent | 75ca06526a29dfac447265a52014305fb96d7ebf (diff) | |
| download | yosys-dfb242c905ff10bb4038f080aeb74a820e8fbd00.tar.gz yosys-dfb242c905ff10bb4038f080aeb74a820e8fbd00.tar.bz2 yosys-dfb242c905ff10bb4038f080aeb74a820e8fbd00.zip | |
Add "read_ilang -lib"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 52496e702..fb045bc72 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -976,6 +976,7 @@ public: virtual void sort(); virtual void check(); virtual void optimize(); + virtual void makeblackbox(); void connect(const RTLIL::SigSig &conn); void connect(const RTLIL::SigSpec &lhs, const RTLIL::SigSpec &rhs); |