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| author | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-01-05 13:28:45 +0100 |
| commit | c80315cea42414216bcc7b62acb2ef9a41b54eab (patch) | |
| tree | bc089997bff5a8d906fc652441fdff803add06dd /kernel/rtlil.h | |
| parent | fefb652d568749731b581185e6cb201f0fff479e (diff) | |
| download | yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.gz yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.tar.bz2 yosys-c80315cea42414216bcc7b62acb2ef9a41b54eab.zip | |
Bugfix in hierarchy handling of blackbox module ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index fc29e1e65..a251b4252 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -906,7 +906,7 @@ public: Module(); virtual ~Module(); - virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); virtual void sort(); |