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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 14:13:36 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2016-06-18 14:23:38 +0200 |
| commit | a8200a773fb8cf2ce2d8793716b62e01c97dd731 (patch) | |
| tree | 45fde92e3cdd9d6bd1585fbdcc6e04076fbb4b9a /kernel/rtlil.h | |
| parent | 178ff3e7f6f9766f0b1a3e8dcc96e030aea59b15 (diff) | |
| download | yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.tar.gz yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.tar.bz2 yosys-a8200a773fb8cf2ce2d8793716b62e01c97dd731.zip | |
A few modifications after pull request comments
- Renamed Design::packages to Design::verilog_packages
- No need to include ast.h in rtlil.h
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 275ba6820..274f97023 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -18,7 +18,6 @@ */ #include "kernel/yosys.h" -#include "frontends/ast/ast.h" #ifndef RTLIL_H #define RTLIL_H @@ -793,7 +792,7 @@ struct RTLIL::Design int refcount_modules_; dict<RTLIL::IdString, RTLIL::Module*> modules_; - std::vector<AST::AstNode*> packages; + std::vector<AST::AstNode*> verilog_packages; std::vector<RTLIL::Selection> selection_stack; dict<RTLIL::IdString, RTLIL::Selection> selection_vars; |