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author | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2015-10-24 22:56:40 +0200 |
commit | 7f110e7018d35f29cf6a5d3031400a8044c8d32d (patch) | |
tree | 9c65e6929e43faec716efab17b37bd53f9afa4b3 /kernel/rtlil.h | |
parent | 6af80769678f260aa4aeaf3b12b54dfdc15fa5dd (diff) | |
download | yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.gz yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.tar.bz2 yosys-7f110e7018d35f29cf6a5d3031400a8044c8d32d.zip |
renamed SigSpec::to_single_sigbit() to SigSpec::as_bit(), added is_bit()
Diffstat (limited to 'kernel/rtlil.h')
-rw-r--r-- | kernel/rtlil.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 43ef58068..99dcb3116 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -690,6 +690,7 @@ public: bool is_wire() const; bool is_chunk() const; + inline bool is_bit() const { return width_ == 1; } bool is_fully_const() const; bool is_fully_zero() const; @@ -704,6 +705,7 @@ public: RTLIL::Const as_const() const; RTLIL::Wire *as_wire() const; RTLIL::SigChunk as_chunk() const; + RTLIL::SigBit as_bit() const; bool match(std::string pattern) const; @@ -712,7 +714,6 @@ public: std::vector<RTLIL::SigBit> to_sigbit_vector() const; std::map<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_map(const RTLIL::SigSpec &other) const; dict<RTLIL::SigBit, RTLIL::SigBit> to_sigbit_dict(const RTLIL::SigSpec &other) const; - RTLIL::SigBit to_single_sigbit() const; static bool parse(RTLIL::SigSpec &sig, RTLIL::Module *module, std::string str); static bool parse_sel(RTLIL::SigSpec &sig, RTLIL::Design *design, RTLIL::Module *module, std::string str); |