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| author | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2018-02-23 13:14:47 +0100 |
| commit | eb67a7532bf1d8195216257a2d6d301c03980591 (patch) | |
| tree | f9246e5ace86c1cc365b4f5111061d99fbcc9aeb /kernel/rtlil.h | |
| parent | 2521ed305e9d48929c9ede93b8cb0069739408f5 (diff) | |
| download | yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.gz yosys-eb67a7532bf1d8195216257a2d6d301c03980591.tar.bz2 yosys-eb67a7532bf1d8195216257a2d6d301c03980591.zip | |
Add $allconst and $allseq cell types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index a251b4252..54d0b8c22 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1127,6 +1127,8 @@ public: RTLIL::SigSpec Anyconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Anyseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); + RTLIL::SigSpec Allconst (RTLIL::IdString name, int width = 1, const std::string &src = ""); + RTLIL::SigSpec Allseq (RTLIL::IdString name, int width = 1, const std::string &src = ""); RTLIL::SigSpec Initstate (RTLIL::IdString name, const std::string &src = ""); }; |