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| author | whitequark <whitequark@whitequark.org> | 2018-12-23 09:04:23 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2018-12-23 09:04:30 +0000 |
| commit | 18291c20d2b17689729d9c36b08967e928e4e32a (patch) | |
| tree | 12137ac745879d7f4c9c9d00b6285b9a3f6c7d86 /kernel/rtlil.h | |
| parent | b784440857d6b71f46ae8784cc3767962e4edcaa (diff) | |
| download | yosys-18291c20d2b17689729d9c36b08967e928e4e32a.tar.gz yosys-18291c20d2b17689729d9c36b08967e928e4e32a.tar.bz2 yosys-18291c20d2b17689729d9c36b08967e928e4e32a.zip | |
proc_clean: remove any empty cases if all cases use all-def compare.
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 276540aa1..f877622aa 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1227,6 +1227,8 @@ struct RTLIL::CaseRule ~CaseRule(); void optimize(); + bool empty() const; + template<typename T> void rewrite_sigspecs(T &functor); RTLIL::CaseRule *clone() const; }; @@ -1238,6 +1240,8 @@ struct RTLIL::SwitchRule : public RTLIL::AttrObject ~SwitchRule(); + bool empty() const; + template<typename T> void rewrite_sigspecs(T &functor); RTLIL::SwitchRule *clone() const; }; |