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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-11 23:33:31 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:36 +0200 |
| commit | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (patch) | |
| tree | e8d3be5d6134dbf4fc26b47f9481f80a4bdfc4c7 /kernel/rtlil.h | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.gz yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.bz2 yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.zip | |
Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 027faf416..8a2b0a4f3 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -907,7 +907,9 @@ public: Module(); virtual ~Module(); virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, bool mayfail = false); + virtual RTLIL::IdString derive(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Const> parameters, dict<RTLIL::IdString, RTLIL::Module*> interfaces, bool mayfail = false); virtual size_t count_id(RTLIL::IdString id); + virtual void reprocess_module(RTLIL::Design *design, dict<RTLIL::IdString, RTLIL::Module *> local_interfaces); virtual void sort(); virtual void check(); |