| Commit message (Expand) | Author | Age | Files | Lines |
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| * | Add YOSYS_NO_IDS_REFCNT configuration macro | Clifford Wolf | 2019-08-11 | 1 | -1/+22 |
| * | Use ID() in kernel/*, add simple ID:: hack (to be improved upon later) | Clifford Wolf | 2019-08-11 | 1 | -3/+11 |
| * | More improvements and cleanups in IdString subsystem | Clifford Wolf | 2019-08-11 | 1 | -36/+52 |
| * | RTLIL::S{0,1} -> State::S{0,1} for headers | Eddie Hung | 2019-08-07 | 1 | -1/+1 |
| * | Merge remote-tracking branch 'origin/master' into eddie/cleanup | Eddie Hung | 2019-08-07 | 1 | -0/+2 |
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| | * | Add SigSpec::extract_end() convenience function | Eddie Hung | 2019-08-06 | 1 | -0/+1 |
| | * | Merge remote-tracking branch 'origin/master' into eddie/wreduce_add | Eddie Hung | 2019-08-06 | 1 | -3/+21 |
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| | * | | Add an SigSpec::at(offset, defval) convenience method | Eddie Hung | 2019-07-19 | 1 | -0/+1 |
| * | | | Fix typos | Eddie Hung | 2019-08-06 | 1 | -2/+2 |
| * | | | Use IdString::begins_with() | Eddie Hung | 2019-08-06 | 1 | -3/+7 |
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| * | | Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs | Clifford Wolf | 2019-08-06 | 1 | -0/+2 |
| * | | replaced std::iterator with using statements | Jakob Wenzel | 2019-07-25 | 1 | -6/+6 |
| * | | made ObjectIterator extend std::iterator | Jakob Wenzel | 2019-07-24 | 1 | -2/+18 |
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| * | Allow attributes on individual switch cases in RTLIL. | whitequark | 2019-07-08 | 1 | -1/+1 |
| * | Undo iterator based Module::remove() for cells, as containers will not | Eddie Hung | 2019-06-27 | 1 | -1/+0 |
| * | Fix leak removing cells during ABC integration; also preserve attr | Eddie Hung | 2019-06-17 | 1 | -0/+1 |
| * | Further cleanup based on @daveshah1 | Eddie Hung | 2019-06-14 | 1 | -0/+6 |
| * | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-06-12 | 1 | -1/+65 |
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| | * | Refactor hierarchy wand/wor handling | Clifford Wolf | 2019-05-28 | 1 | -0/+1 |
| | * | Add rewrite_sigspecs2, Improve remove() wires | Clifford Wolf | 2019-05-15 | 1 | -0/+60 |
| | * | Merge pull request #991 from kristofferkoch/gcc9-warnings | Clifford Wolf | 2019-05-08 | 1 | -0/+3 |
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| | | * | Fix all warnings that occurred when compiling with gcc9 | Kristoffer Ellersgaard Koch | 2019-05-08 | 1 | -0/+3 |
| | * | | Improve write_verilog specify support | Clifford Wolf | 2019-05-04 | 1 | -1/+1 |
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| * | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-22 | 1 | -1/+26 |
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| | * | Merge pull request #905 from christian-krieg/feature/python_bindings | Clifford Wolf | 2019-04-22 | 1 | -1/+26 |
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| | | * | Merge remote-tracking branch 'origin/master' into feature/python_bindings | Benedikt Tutzer | 2019-03-28 | 1 | -6/+74 |
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| | | * | | Deleted duplicate Destructor | Benedikt Tutzer | 2018-08-21 | 1 | -1/+0 |
| | | * | | added some checks if python is enabled to make sure everything compiles if py... | Benedikt Tutzer | 2018-08-20 | 1 | -0/+1 |
| | | * | | Added Wrappers for: | Benedikt Tutzer | 2018-08-13 | 1 | -3/+11 |
| | | * | | added destructors for wires and cells | Benedikt Tutzer | 2018-07-10 | 1 | -1/+2 |
| | | * | | multiple designs can now exist independent from each other. Cells/Wires/Modul... | Benedikt Tutzer | 2018-07-09 | 1 | -0/+16 |
| * | | | | Merge remote-tracking branch 'origin/master' into xaig | Eddie Hung | 2019-04-20 | 1 | -1/+1 |
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| | * | | | Add "wbflip" command | Clifford Wolf | 2019-04-20 | 1 | -1/+1 |
| | * | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 |
| * | | | | Ignore 'whitebox' attr in flatten with "-wb" option | Eddie Hung | 2019-04-18 | 1 | -2/+2 |
| * | | | | Merge remote-tracking branch 'origin/clifford/whitebox' into xaig | Eddie Hung | 2019-04-18 | 1 | -0/+4 |
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| | * | | | Add "whitebox" attribute, add "read_verilog -wb" | Clifford Wolf | 2019-04-18 | 1 | -0/+4 |
| * | | | | Merge branch 'master' into xaig | Eddie Hung | 2019-04-08 | 1 | -5/+68 |
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| | * | | | Add "read_ilang -lib" | Clifford Wolf | 2019-04-05 | 1 | -0/+1 |
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| | * | | Add RTLIL::Const::ext[su](), fix RTLIL::SigSpec::extend_u0 for 0-size signals | Clifford Wolf | 2019-03-23 | 1 | -0/+8 |
| | * | | Improve determinism of IdString DB for similar scripts | Clifford Wolf | 2019-03-11 | 1 | -5/+59 |
| * | | | Add IdString::ends_with() | Eddie Hung | 2019-02-26 | 1 | -0/+6 |
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| * | | proc_clean: remove any empty cases if all cases use all-def compare. | whitequark | 2018-12-23 | 1 | -0/+4 |
| * | | Support for 'modports' for System Verilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -1/+1 |
| * | | Synthesis support for SystemVerilog interfaces | Ruben Undheim | 2018-10-12 | 1 | -0/+2 |
| * | | Consistent use of 'override' for virtual methods in derived classes. | Henner Zeller | 2018-07-20 | 1 | -1/+1 |
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| * | Add $allconst and $allseq cell types | Clifford Wolf | 2018-02-23 | 1 | -0/+2 |
| * | Bugfix in hierarchy handling of blackbox module ports | Clifford Wolf | 2018-01-05 | 1 | -1/+1 |
| * | Add RTLIL::Const::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+1 |
| * | Add SigSpec::is_fully_ones() | Clifford Wolf | 2017-12-14 | 1 | -0/+1 |
