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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:54:24 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-17 12:54:24 -0700 |
| commit | b45d06d7a334c4b18e44793b33aaffcaf1f04b21 (patch) | |
| tree | ea80de203f95ea9e745306d255d1ed7ae481e6df /kernel/rtlil.h | |
| parent | c15ee827f4a171abe3108dba8f9ad0d7078eb306 (diff) | |
| download | yosys-b45d06d7a334c4b18e44793b33aaffcaf1f04b21.tar.gz yosys-b45d06d7a334c4b18e44793b33aaffcaf1f04b21.tar.bz2 yosys-b45d06d7a334c4b18e44793b33aaffcaf1f04b21.zip | |
Fix leak removing cells during ABC integration; also preserve attr
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index f4fcf5dcf..4a0f8b4f8 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1040,6 +1040,7 @@ public: // Removing wires is expensive. If you have to remove wires, remove them all at once. void remove(const pool<RTLIL::Wire*> &wires); void remove(RTLIL::Cell *cell); + dict<RTLIL::IdString, RTLIL::Cell*>::iterator remove(dict<RTLIL::IdString, RTLIL::Cell*>::iterator it); void rename(RTLIL::Wire *wire, RTLIL::IdString new_name); void rename(RTLIL::Cell *cell, RTLIL::IdString new_name); |