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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:14:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-07 11:14:03 -0700 |
| commit | 71eff6f0deae3ffaf75cca22768b66a2dc918b3e (patch) | |
| tree | 7bc05d412a20985e701abc2607bd2d682c5fcb83 /kernel/rtlil.h | |
| parent | 71649969213863b2695f1c51956886fc7879c3e6 (diff) | |
| download | yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.tar.gz yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.tar.bz2 yosys-71eff6f0deae3ffaf75cca22768b66a2dc918b3e.zip | |
RTLIL::S{0,1} -> State::S{0,1} for headers
Diffstat (limited to 'kernel/rtlil.h')
| -rw-r--r-- | kernel/rtlil.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 99c683974..37b5f984c 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -1408,7 +1408,7 @@ struct RTLIL::Process : public RTLIL::AttrObject inline RTLIL::SigBit::SigBit() : wire(NULL), data(RTLIL::State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::State bit) : wire(NULL), data(bit) { } -inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? RTLIL::S1 : RTLIL::S0) { } +inline RTLIL::SigBit::SigBit(bool bit) : wire(NULL), data(bit ? State::S1 : State::S0) { } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire) : wire(wire), offset(0) { log_assert(wire && wire->width == 1); } inline RTLIL::SigBit::SigBit(RTLIL::Wire *wire, int offset) : wire(wire), offset(offset) { log_assert(wire != nullptr); } inline RTLIL::SigBit::SigBit(const RTLIL::SigChunk &chunk) : wire(chunk.wire) { log_assert(chunk.width == 1); if (wire) offset = chunk.offset; else data = chunk.data[0]; } |