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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2021-10-19 18:43:30 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
| commit | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (patch) | |
| tree | b55271d7943d0a2482a3a3cbc708ed30bc8d5af2 /kernel/rtlil.cc | |
| parent | ee230f2bb9a2fe473b0ddb6bcfa30a15b0f07c88 (diff) | |
| download | yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.gz yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.tar.bz2 yosys-bd16d01c0eed5c96a241e6ee9e56b8f7890319a1.zip | |
Split out logic for reprocessing an AstModule
This will enable other features to use same core logic for replacing an
existing AstModule with a newly elaborated version.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 3778972bc..9fac57523 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -936,9 +936,9 @@ void RTLIL::Module::makeblackbox() set_bool_attribute(ID::blackbox); } -void RTLIL::Module::reprocess_module(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &) +void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdString, RTLIL::Module *> &) { - log_error("Cannot reprocess_module module `%s' !\n", id2cstr(name)); + log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name)); } RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail) |