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| author | whitequark <whitequark@whitequark.org> | 2020-08-26 17:29:32 +0000 |
|---|---|---|
| committer | whitequark <whitequark@whitequark.org> | 2020-08-26 17:29:32 +0000 |
| commit | 00e7dec7f54eb2e4f18112e5c0007a55287fdf8e (patch) | |
| tree | e0db11dfa158264e270f30e2b677e319f09b6047 /kernel/rtlil.cc | |
| parent | 4f2b78e19af3a2d342efe9780e220282b7a3a046 (diff) | |
| download | yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.tar.gz yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.tar.bz2 yosys-00e7dec7f54eb2e4f18112e5c0007a55287fdf8e.zip | |
Replace "ILANG" with "RTLIL" everywhere.
The only difference between "RTLIL" and "ILANG" is that the latter is
the text representation of the former, as opposed to the in-memory
graph representation. This distinction serves no purpose but confuses
people: it is not obvious that the ILANG backend writes RTLIL graphs.
Passes `write_ilang` and `read_ilang` are provided as aliases to
`write_rtlil` and `read_rtlil` for compatibility.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index c56f0dcab..a9f585616 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -22,7 +22,7 @@ #include "kernel/celltypes.h" #include "frontends/verilog/verilog_frontend.h" #include "frontends/verilog/preproc.h" -#include "backends/ilang/ilang_backend.h" +#include "backends/rtlil/rtlil_backend.h" #include <string.h> #include <algorithm> @@ -923,7 +923,7 @@ namespace { void error(int linenr) { std::stringstream buf; - ILANG_BACKEND::dump_cell(buf, " ", cell); + RTLIL_BACKEND::dump_cell(buf, " ", cell); log_error("Found error in internal cell %s%s%s (%s) at %s:%d:\n%s", module ? module->name.c_str() : "", module ? "." : "", |