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| author | clairexen <claire@symbioticeda.com> | 2020-06-08 15:27:15 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-06-08 15:27:15 +0200 |
| commit | fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd (patch) | |
| tree | 53480c2d71083790474ec7c70659f96874b77d60 /kernel/rtlil.cc | |
| parent | f57524cf713e2cdc368ded8b7e13f85d310b8749 (diff) | |
| parent | 5a5a9b4ffe8b38eca7dc4fdfc56a16d401022fa2 (diff) | |
| download | yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.tar.gz yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.tar.bz2 yosys-fbd0d8d5f0c4d1dc1fc35371adc6d89efd2534cd.zip | |
Merge pull request #2105 from whitequark/split-flatten-off-techmap
Split `flatten` from `techmap` and simplify it
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 397edc4e7..109113370 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1885,6 +1885,18 @@ RTLIL::Cell *RTLIL::Module::addCell(RTLIL::IdString name, const RTLIL::Cell *oth return cell; } +RTLIL::Memory *RTLIL::Module::addMemory(RTLIL::IdString name, const RTLIL::Memory *other) +{ + RTLIL::Memory *mem = new RTLIL::Memory; + mem->name = name; + mem->width = other->width; + mem->start_offset = other->start_offset; + mem->size = other->size; + mem->attributes = other->attributes; + memories[mem->name] = mem; + return mem; +} + #define DEF_METHOD(_func, _y_size, _type) \ RTLIL::Cell* RTLIL::Module::add ## _func(RTLIL::IdString name, const RTLIL::SigSpec &sig_a, const RTLIL::SigSpec &sig_y, bool is_signed, const std::string &src) { \ RTLIL::Cell *cell = addCell(name, _type); \ |