diff options
| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-21 02:26:52 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-07-28 23:18:38 +0200 |
| commit | 19720b970dff017c47805e37745b9fcf29843c45 (patch) | |
| tree | b5a56d888b9e8c7530fc456a8748c32bb3feaed3 /kernel/rtlil.cc | |
| parent | 37d76deef1229048e145d77b5c75bcc2e0e1cf44 (diff) | |
| download | yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.gz yosys-19720b970dff017c47805e37745b9fcf29843c45.tar.bz2 yosys-19720b970dff017c47805e37745b9fcf29843c45.zip | |
memory: Introduce $meminit_v2 cell, with EN input.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 21ee15ac5..bd6b3ad05 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1414,6 +1414,16 @@ namespace { return; } + if (cell->type == ID($meminit_v2)) { + param(ID::MEMID); + param(ID::PRIORITY); + port(ID::ADDR, param(ID::ABITS)); + port(ID::DATA, param(ID::WIDTH) * param(ID::WORDS)); + port(ID::EN, param(ID::WIDTH)); + check_expected(); + return; + } + if (cell->type == ID($mem)) { param(ID::MEMID); param(ID::SIZE); @@ -3177,7 +3187,7 @@ void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) bool RTLIL::Cell::has_memid() const { - return type.in(ID($memwr), ID($memrd), ID($meminit)); + return type.in(ID($memwr), ID($memrd), ID($meminit), ID($meminit_v2)); } bool RTLIL::Cell::is_mem_cell() const |