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author | whitequark <whitequark@whitequark.org> | 2020-06-04 11:23:06 +0000 |
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committer | GitHub <noreply@github.com> | 2020-06-04 11:23:06 +0000 |
commit | 3bffd09d6423b70ca154527c363985ff048f807d (patch) | |
tree | 5d38c0618e478722d8dcd0fb681ef443869f0b8c /kernel/rtlil.cc | |
parent | 44f1e651558c5063b6e0c4496d916abc23329751 (diff) | |
parent | adb483ddfd3163a4efa08e09a35dd926377aa71d (diff) | |
download | yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.gz yosys-3bffd09d6423b70ca154527c363985ff048f807d.tar.bz2 yosys-3bffd09d6423b70ca154527c363985ff048f807d.zip |
Merge pull request #2006 from jersey99/signed-in-rtlil-wire
Preserve 'signed'-ness of a verilog wire through RTLIL
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index ca4201b53..397edc4e7 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -1862,6 +1862,7 @@ RTLIL::Wire *RTLIL::Module::addWire(RTLIL::IdString name, const RTLIL::Wire *oth wire->port_input = other->port_input; wire->port_output = other->port_output; wire->upto = other->upto; + wire->is_signed = other->is_signed; wire->attributes = other->attributes; return wire; } @@ -2447,6 +2448,7 @@ RTLIL::Wire::Wire() port_input = false; port_output = false; upto = false; + is_signed = false; #ifdef WITH_PYTHON RTLIL::Wire::get_all_wires()->insert(std::pair<unsigned int, RTLIL::Wire*>(hashidx_, this)); |