diff options
| author | Zachary Snow <zach@zachjs.com> | 2021-10-19 18:46:26 -0600 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-10-25 18:25:50 -0700 |
| commit | e833c6a418103feb30f0cc3e5c482da00ee9f820 (patch) | |
| tree | ef7d028ed17200f04558f3d2426f3db7ef6134cd /kernel/rtlil.cc | |
| parent | bd16d01c0eed5c96a241e6ee9e56b8f7890319a1 (diff) | |
| download | yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.gz yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.tar.bz2 yosys-e833c6a418103feb30f0cc3e5c482da00ee9f820.zip | |
verilog: use derived module info to elaborate cell connections
- Attempt to lookup a derived module if it potentially contains a port
connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
connections in a future change
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 9fac57523..88153a380 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -941,6 +941,11 @@ void RTLIL::Module::expand_interfaces(RTLIL::Design *, const dict<RTLIL::IdStrin log_error("Class doesn't support expand_interfaces (module: `%s')!\n", id2cstr(name)); } +bool RTLIL::Module::reprocess_if_necessary(RTLIL::Design *) +{ + return false; +} + RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString, RTLIL::Const> &, bool mayfail) { if (mayfail) |