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| author | Rupert Swarbrick <rswarbrick@gmail.com> | 2020-04-20 15:58:30 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-06-14 12:06:08 -0400 |
| commit | 081111714eed9cbc3dacac766cad85de30e98073 (patch) | |
| tree | a9b13a2f3a1aa7391bd815f98bdfa2b3963b4f52 /kernel/rtlil.cc | |
| parent | 801ecc0e1d75f092981361632265edce67130a73 (diff) | |
| download | yosys-081111714eed9cbc3dacac766cad85de30e98073.tar.gz yosys-081111714eed9cbc3dacac766cad85de30e98073.tar.bz2 yosys-081111714eed9cbc3dacac766cad85de30e98073.zip | |
Simplify some RTLIL destructors
No change in behaviour, but use range-based for loops instead of
iterators.
Diffstat (limited to 'kernel/rtlil.cc')
| -rw-r--r-- | kernel/rtlil.cc | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index a756218f3..b7bef723f 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -571,8 +571,8 @@ RTLIL::Design::Design() RTLIL::Design::~Design() { - for (auto it = modules_.begin(); it != modules_.end(); ++it) - delete it->second; + for (auto &pr : modules_) + delete pr.second; for (auto n : verilog_packages) delete n; for (auto n : verilog_globals) @@ -864,14 +864,14 @@ RTLIL::Module::Module() RTLIL::Module::~Module() { - for (auto it = wires_.begin(); it != wires_.end(); ++it) - delete it->second; - for (auto it = memories.begin(); it != memories.end(); ++it) - delete it->second; - for (auto it = cells_.begin(); it != cells_.end(); ++it) - delete it->second; - for (auto it = processes.begin(); it != processes.end(); ++it) - delete it->second; + for (auto &pr : wires_) + delete pr.second; + for (auto &pr : memories) + delete pr.second; + for (auto &pr : cells_) + delete pr.second; + for (auto &pr : processes) + delete pr.second; #ifdef WITH_PYTHON RTLIL::Module::get_all_modules()->erase(hashidx_); #endif |