iCE40/yosys - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
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*	Added support for hierarchical defparams	Clifford Wolf	2016-11-15	3	-16/+41
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*	Remember global declarations and defines accross read_verilog calls	Clifford Wolf	2016-11-15	4	-7/+19
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*	Fixed anonymous genblock object names	Clifford Wolf	2016-11-04	1	-1/+1
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*	Some fixes in handling of signed arrays	Clifford Wolf	2016-11-01	2	-0/+7
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*	Added avail params to ilang format, check module params in 'hierarchy -check'	Clifford Wolf	2016-10-22	2	-3/+14
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*	No limit for length of lines in BLIF front-end	Clifford Wolf	2016-10-19	1	-1/+7
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*	Added $anyseq cell type	Clifford Wolf	2016-10-14	3	-5/+5
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*	Added $global_clock verilog syntax support for creating $ff cells	Clifford Wolf	2016-10-14	3	-5/+19
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*	Added $ff and $_FF_ cell types	Clifford Wolf	2016-10-12	1	-4/+8
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*	Added liberty parser support for types within cell decls	Clifford Wolf	2016-09-23	1	-39/+46
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*	Added $past, $stable, $rose, $fell SVA functions	Clifford Wolf	2016-09-19	2	-2/+141
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*	Added support for bus interfaces to "read_liberty -lib"	Clifford Wolf	2016-09-18	1	-1/+77
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*	Added assertpmux	Clifford Wolf	2016-09-07	1	-0/+1
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*	Bugfix in parsing of BLIF latch init values	Clifford Wolf	2016-09-06	1	-1/+1
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*	Avoid creation of bogus initial blocks for assert/assume in always @*	Clifford Wolf	2016-09-06	3	-1/+13
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*	Added $anyconst support to yosys-smtbmc	Clifford Wolf	2016-08-30	1	-0/+2
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*	Removed $aconst cell type	Clifford Wolf	2016-08-30	3	-6/+6
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*	Removed $predict again	Clifford Wolf	2016-08-28	6	-14/+3
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*	Added read_verilog -norestrict -assume-asserts	Clifford Wolf	2016-08-26	4	-5/+40
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*	Improved verilog parser errors	Clifford Wolf	2016-08-25	1	-0/+3
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*	Added SV "restrict" keyword	Clifford Wolf	2016-08-24	1	-1/+2
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*	Fixed bug with memories that do not have a down-to-zero data width	Clifford Wolf	2016-08-22	1	-2/+13
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*	Another bugfix in mem2reg code	Clifford Wolf	2016-08-21	3	-7/+31
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*	Minor improvements to AstNode::dumpAst() and AstNode::dumpVlog()	Clifford Wolf	2016-08-21	1	-4/+15
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*	Fixed finish_addr handling in $readmemh/$readmemb	Clifford Wolf	2016-08-20	1	-3/+3
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*	Optimize memory address port width in wreduce and memory_collect, not ↵	Clifford Wolf	2016-08-19	2	-4/+13
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*	Only allow posedge/negedge with 1 bit wide signals	Clifford Wolf	2016-08-10	1	-0/+2
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*	Fixed bug in parsing real constants	Clifford Wolf	2016-08-06	1	-4/+4
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*	Added $anyconst and $aconst	Clifford Wolf	2016-07-27	3	-1/+50
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*	Added "read_verilog -dump_rtlil"	Clifford Wolf	2016-07-27	3	-9/+30
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*	Fixed a verilog parser memory leak	Clifford Wolf	2016-07-25	1	-0/+1
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*	Fixed parsing of empty positional cell ports	Clifford Wolf	2016-07-25	1	-2/+31
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*	No tristate warning message for "read_verilog -lib"	Clifford Wolf	2016-07-23	3	-8/+11
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*	Using $initstate in "initial assume" and "initial assert"	Clifford Wolf	2016-07-21	1	-1/+6
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*	Added $initstate cell type and vlog function	Clifford Wolf	2016-07-21	2	-0/+26
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*	After reading the SV spec, using non-standard predict() instead of expect()	Clifford Wolf	2016-07-21	6	-12/+16
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*	Added basic support for $expect cells	Clifford Wolf	2016-07-13	6	-8/+25
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*	Fixed mem assignment in left-hand-side concatenation	Clifford Wolf	2016-07-08	1	-0/+44
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*	Allow defining input ports as "input logic" in SystemVerilog	Ruben Undheim	2016-06-20	1	-2/+2
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*	Merge branch 'sv_packages' of https://github.com/rubund/yosys	Clifford Wolf	2016-06-19	5	-1/+49
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\| *	A few modifications after pull request comments	Ruben Undheim	2016-06-18	1	-2/+2
\| \| \| \| \| \| \| \| \| \|	- Renamed Design::packages to Design::verilog_packages - No need to include ast.h in rtlil.h
\| *	Added support for SystemVerilog packages with localparam definitions	Ruben Undheim	2016-06-18	5	-1/+49
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* \|	Added "read_blif -sop"	Clifford Wolf	2016-06-18	1	-5/+10
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*	Added $sop cell type and "abc -sop"	Clifford Wolf	2016-06-17	2	-24/+80
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*	Fixed procedural assignments to non-unique lvalues, e.g. {y,y} = {a,b}	Clifford Wolf	2016-05-27	1	-0/+11
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*	Fixed access-after-delete bug in mem2reg code	Clifford Wolf	2016-05-27	2	-6/+23
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*	fixed typos in error messages	Clifford Wolf	2016-05-27	1	-3/+3
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*	Small improvements in Verilog front-end docs	Clifford Wolf	2016-05-20	1	-0/+3
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*	Include <cmath> in yosys.h	Clifford Wolf	2016-05-08	1	-9/+0
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*	Added support for "active high" and "active low" latches in BLIF front-end	Clifford Wolf	2016-04-22	1	-0/+4
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