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authorJannis Harder <me@jix.one>2022-08-09 15:43:26 +0200
committerJannis Harder <me@jix.one>2022-08-16 13:37:30 +0200
commitf7023d06a2bda56467c8f07cc44d3b92f0eab2ba (patch)
treeab23fa7355df8f8ead24839ee7846e68cdbfb935 /CHANGELOG
parent66f761a8c54b66b8e6b4667cfb54072ad76952e0 (diff)
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sim: -hdlname option to preserve flattened hierarchy in sim output
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diff --git a/CHANGELOG b/CHANGELOG
index 6403c5b9a..a1f4624ee 100644
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+++ b/CHANGELOG
@@ -9,6 +9,8 @@ Yosys 0.20 .. Yosys 0.20-dev
- Added option "-formal" to "memory_map" pass
- Added option "-witness" to "rename" - give public names to all signals
present in yosys witness traces
+ - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
+ simulation output for a flattened design
* Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained