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| author | Jannis Harder <me@jix.one> | 2022-08-09 15:43:26 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-08-16 13:37:30 +0200 |
| commit | f7023d06a2bda56467c8f07cc44d3b92f0eab2ba (patch) | |
| tree | ab23fa7355df8f8ead24839ee7846e68cdbfb935 /CHANGELOG | |
| parent | 66f761a8c54b66b8e6b4667cfb54072ad76952e0 (diff) | |
| download | yosys-f7023d06a2bda56467c8f07cc44d3b92f0eab2ba.tar.gz yosys-f7023d06a2bda56467c8f07cc44d3b92f0eab2ba.tar.bz2 yosys-f7023d06a2bda56467c8f07cc44d3b92f0eab2ba.zip | |
sim: -hdlname option to preserve flattened hierarchy in sim output
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -9,6 +9,8 @@ Yosys 0.20 .. Yosys 0.20-dev - Added option "-formal" to "memory_map" pass - Added option "-witness" to "rename" - give public names to all signals present in yosys witness traces + - Added option "-hdlname" to "sim" pass - preserves hiearachy when writing + simulation output for a flattened design * Formal Verification - Added $anyinit cell to directly represent FFs with an unconstrained |