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authorMiodrag Milanovic <mmicko@gmail.com>2022-09-06 08:22:23 +0200
committerMiodrag Milanovic <mmicko@gmail.com>2022-09-06 08:22:23 +0200
commit0ff129c10b68c8d0cec850694e7264791560d46d (patch)
tree7705f9094579550de23b07f21730ff9caaa0c8b6 /CHANGELOG
parent6d5adb6a65d8a2c224f16cd3c8c5ede173223e29 (diff)
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Update Changelog
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@@ -11,6 +11,7 @@ Yosys 0.20 .. Yosys 0.20-dev
present in yosys witness traces
- Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
simulation output for a flattened design
+ - Addded option "-scramble-name" to "rename" pass
* Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained
@@ -23,6 +24,18 @@ Yosys 0.20 .. Yosys 0.20-dev
conversion.
- yosys-witness: Conversion from and to AIGER witness traces.
+ * Verific support
+ - Filename re-writing support for "verific" pass.
+
+ * Various
+ - ABC performance improvements
+ - Filename re-writing added for "show -lib".
+
+ * SmartFusion2 support
+ - Added $alu support
+ - Added SYSRESET and XTLOSC cells
+ - Compatible now with LiberoSoc flow
+
Yosys 0.19 .. Yosys 0.20
--------------------------
* New commands and options