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authorJannis Harder <me@jix.one>2022-08-02 16:07:28 +0200
committerJannis Harder <me@jix.one>2022-08-16 13:37:30 +0200
commita2f9ebe43a287233917947851e0d0dff803a4675 (patch)
tree88e1730c528e1e04702e9ad1281005770853a5e7 /CHANGELOG
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memory_map: Add -formal option
This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.
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diff --git a/CHANGELOG b/CHANGELOG
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@@ -6,6 +6,7 @@ Yosys 0.20 .. Yosys 0.20-dev
--------------------------
* New commands and options
- Added "formalff" pass - transforms FFs for formal verification
+ - Added option "-formal" to "memory_map" pass
* Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained