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| author | Jannis Harder <me@jix.one> | 2022-08-02 16:07:28 +0200 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2022-08-16 13:37:30 +0200 |
| commit | a2f9ebe43a287233917947851e0d0dff803a4675 (patch) | |
| tree | 88e1730c528e1e04702e9ad1281005770853a5e7 /CHANGELOG | |
| parent | 0cdb14df41be53f770390d6ad01cf650f1bc49da (diff) | |
| download | yosys-a2f9ebe43a287233917947851e0d0dff803a4675.tar.gz yosys-a2f9ebe43a287233917947851e0d0dff803a4675.tar.bz2 yosys-a2f9ebe43a287233917947851e0d0dff803a4675.zip | |
memory_map: Add -formal option
This maps memories for a global clock based formal verification flow.
This implies -keepdc, uses $ff cells for ROMs and sets hdlname
attributes.
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -6,6 +6,7 @@ Yosys 0.20 .. Yosys 0.20-dev -------------------------- * New commands and options - Added "formalff" pass - transforms FFs for formal verification + - Added option "-formal" to "memory_map" pass * Formal Verification - Added $anyinit cell to directly represent FFs with an unconstrained |