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path:
root
/
techlibs
/
xilinx
/
cells_sim.v
Commit message (
Expand
)
Author
Age
Files
Lines
*
Put attributes above port
Eddie Hung
2019-08-23
1
-19
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+46
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Merge remote-tracking branch 'origin/master' into xaig_arrival
Eddie Hung
2019-08-23
1
-5
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+10
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Forgot one
Eddie Hung
2019-08-23
1
-1
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+2
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Put abc_* attributes above port
Eddie Hung
2019-08-23
1
-7
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+14
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Add abc_arrival to SRL*
Eddie Hung
2019-08-21
1
-3
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+5
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Oops
Eddie Hung
2019-08-20
1
-1
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+1
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xilinx to use abc_map.v with -max_iter 1
Eddie Hung
2019-08-20
1
-3
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+6
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Add reference to FD* timing
Eddie Hung
2019-08-20
1
-0
/
+2
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Remove sequential extension
Eddie Hung
2019-08-20
1
-8
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+16
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Remove SRL* delays from cells_sim.v
Eddie Hung
2019-08-20
1
-5
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+3
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Wrap LUTRAMs in order to capture comb/seq behaviour
Eddie Hung
2019-08-20
1
-15
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+9
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Add LUTRAM delays
Eddie Hung
2019-08-20
1
-3
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+6
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Use abc_{map,unmap,model}.v
Eddie Hung
2019-08-20
1
-8
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+0
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Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung
2019-08-20
1
-2
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+2
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Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithro
Eddie Hung
2019-08-19
1
-2
/
+2
*
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Add arrival times for SRL outputs
Eddie Hung
2019-08-19
1
-3
/
+5
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Attach abc_scc_break, abc_carry_{in,out} attr to ports not modules
Eddie Hung
2019-08-16
1
-8
/
+20
*
xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...
Marcin Kościelnicki
2019-07-11
1
-2
/
+2
*
Revert "Fix broken MUXFx box, use MUXF7x2 box instead"
Eddie Hung
2019-07-01
1
-3
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+3
*
Fix broken MUXFx box, use MUXF7x2 box instead
Eddie Hung
2019-07-01
1
-3
/
+3
*
Fix CARRY4 abc_box_id
Eddie Hung
2019-06-28
1
-1
/
+1
*
Merge remote-tracking branch 'origin/master' into xc7mux
Eddie Hung
2019-06-28
1
-2
/
+2
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*
Refactor for one "abc_carry" attribute on module
Eddie Hung
2019-06-27
1
-2
/
+2
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*
Merge origin/master
Eddie Hung
2019-06-27
1
-1
/
+1
*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-26
1
-3
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+3
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Add "WE" to dist RAM's abc_scc_break
Eddie Hung
2019-06-26
1
-3
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+3
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Add RAM32X1D box info
Eddie Hung
2019-06-25
1
-2
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+3
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Merge remote-tracking branch 'origin/master' into xaig
Eddie Hung
2019-06-25
1
-0
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+17
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Merge remote-tracking branch 'origin/eddie/fix1132' into xc7mux
Eddie Hung
2019-06-26
1
-1
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+1
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Simulation model verilog fix
Miodrag Milanovic
2019-06-26
1
-1
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+1
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Cleanup abc_box_id
Eddie Hung
2019-06-26
1
-5
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+5
*
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Add RAM32X1D box info
Eddie Hung
2019-06-24
1
-2
/
+3
*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-24
1
-0
/
+2
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Add Xilinx dist RAM as comb boxes
Eddie Hung
2019-06-24
1
-0
/
+2
*
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Merge remote-tracking branch 'origin/eddie/ram32x1d' into xc7mux
Eddie Hung
2019-06-24
1
-0
/
+17
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Add RAM32X1D support
Eddie Hung
2019-06-24
1
-0
/
+17
*
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Merge remote-tracking branch 'origin/xaig' into xc7mux
Eddie Hung
2019-06-22
1
-2
/
+0
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Remove DFF and RAMD box info for now
Eddie Hung
2019-06-21
1
-2
/
+0
*
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Add $__XILINX_MUXF78 to preserve entire box
Eddie Hung
2019-06-21
1
-0
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+8
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/
*
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Remove WIP ABC9 flop support
Eddie Hung
2019-06-14
1
-10
/
+10
*
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Disable dist RAM boxes due to comb loop
Eddie Hung
2019-06-11
1
-2
/
+2
*
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Remove #ifndef ABC
Eddie Hung
2019-06-11
1
-4
/
+0
*
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Remove abc_flop attributes for now
Eddie Hung
2019-06-06
1
-56
/
+10
*
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Update abc attributes on FD*E_1
Eddie Hung
2019-06-05
1
-6
/
+26
*
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Typo
Eddie Hung
2019-06-03
1
-1
/
+1
*
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Fix `ifndef
Eddie Hung
2019-06-03
1
-1
/
+1
*
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Add FD*E_1 -> FD*E techmap rules
Eddie Hung
2019-05-31
1
-5
/
+31
*
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Remove whitebox attribute from DRAMs for now
Eddie Hung
2019-05-30
1
-2
/
+2
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Carry in/out to be the last input/output for chains to be preserved
Eddie Hung
2019-05-30
1
-2
/
+2
*
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Re-enable lib_whitebox
Eddie Hung
2019-05-27
1
-5
/
+5
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