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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 13:53:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 13:53:38 -0700 |
| commit | 0079e9b4a677de66372e5c5c9cb011ce74184258 (patch) | |
| tree | 6e967507908ca3e786e0c4187d39770968eb38af /techlibs/xilinx/cells_sim.v | |
| parent | 505d062daf0e2600dacf04cf18d97b279bd58d72 (diff) | |
| download | yosys-0079e9b4a677de66372e5c5c9cb011ce74184258.tar.gz yosys-0079e9b4a677de66372e5c5c9cb011ce74184258.tar.bz2 yosys-0079e9b4a677de66372e5c5c9cb011ce74184258.zip | |
Add LUTRAM delays
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 614fd8eef..fa0a8fea0 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -289,7 +289,8 @@ endmodule (* abc_box_id = 5 *) module RAM32X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, (* abc_scc_break *) input D, input WCLK, (* abc_scc_break *) input WE, @@ -309,7 +310,8 @@ endmodule (* abc_box_id = 6 *) module RAM64X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, (* abc_scc_break *) input D, input WCLK, (* abc_scc_break *) input WE, @@ -329,7 +331,8 @@ endmodule (* abc_box_id = 7 *) module RAM128X1D ( - output DPO, SPO, + // Max delay from: https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLM_R.sdf#L904-L905 + (* abc_arrival=1472 *) output DPO, SPO, (* abc_scc_break *) input D, input WCLK, (* abc_scc_break *) input WE, |