diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-22 19:44:17 -0700 |
| commit | d54dceb547777ab4b489f66554d4c47e867424f9 (patch) | |
| tree | 8e60c03e2a40891b7a078717b8a3c931feb5ae83 /techlibs/xilinx/cells_sim.v | |
| parent | bbf3ad90f59a5b548d263c81ca83ca8f93f1c238 (diff) | |
| parent | 6027549464bf91cee4d4bcbe9586e719dce78c80 (diff) | |
| download | yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.gz yosys-d54dceb547777ab4b489f66554d4c47e867424f9.tar.bz2 yosys-d54dceb547777ab4b489f66554d4c47e867424f9.zip | |
Merge remote-tracking branch 'origin/xaig' into xc7mux
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 3163d8446..8c04d602e 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -289,7 +289,6 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule -//(* abc_box_id = 4 /*, lib_whitebox*/ *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -307,7 +306,6 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -//(* abc_box_id = 5 /*, lib_whitebox*/ *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |