diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:20:15 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-27 11:20:15 -0700 |
| commit | 6c256b8cda66e2ba128d5fa3ba344fe4717711f8 (patch) | |
| tree | b8e0a8c4b21139b46f6919abcfcc0bf6ddee0452 /techlibs/xilinx/cells_sim.v | |
| parent | c226af3f56957cc69b2ce8bb68a8259e26121ddc (diff) | |
| download | yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.tar.gz yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.tar.bz2 yosys-6c256b8cda66e2ba128d5fa3ba344fe4717711f8.zip | |
Merge origin/master
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 4ecf8277b..5fd9973f4 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -286,7 +286,7 @@ module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, input A0, A1, A2, A3, A4, - input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, + input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4 ); parameter INIT = 32'h0; parameter IS_WCLK_INVERTED = 1'b0; |