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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:54:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-25 09:34:19 -0700 |
| commit | 609535739036c30efc35a57730e5ffe968267cdb (patch) | |
| tree | b4c0a4ebff983a55283443e78df932a8db0aaccc /techlibs/xilinx/cells_sim.v | |
| parent | 6f36ec8ecf147f8d669f35dd616714af971db6f4 (diff) | |
| download | yosys-609535739036c30efc35a57730e5ffe968267cdb.tar.gz yosys-609535739036c30efc35a57730e5ffe968267cdb.tar.bz2 yosys-609535739036c30efc35a57730e5ffe968267cdb.zip | |
Add RAM32X1D box info
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 67b221c95..04381e3b9 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -281,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, abc_scc_break="D" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@ -298,7 +299,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 4, abc_scc_break="D" *) +(* abc_box_id = 5, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -316,7 +317,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D" *) +(* abc_box_id = 6, abc_scc_break="D" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |