diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:54:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-24 22:54:35 -0700 |
| commit | e1ba25d79f0fc623006b250e72093199d0804d52 (patch) | |
| tree | 0c29c99e2f2dc58e1b433f5616e9bd434d9a8141 /techlibs/xilinx/cells_sim.v | |
| parent | 1564eb8b549a0927efa4d2b4cbc479038993024a (diff) | |
| download | yosys-e1ba25d79f0fc623006b250e72093199d0804d52.tar.gz yosys-e1ba25d79f0fc623006b250e72093199d0804d52.tar.bz2 yosys-e1ba25d79f0fc623006b250e72093199d0804d52.zip | |
Add RAM32X1D box info
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index c6c49c3cd..e3391da40 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -289,6 +289,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE); always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D; endmodule +(* abc_box_id = 4, abc_scc_break="D" *) module RAM32X1D ( output DPO, SPO, input D, WCLK, WE, @@ -306,7 +307,7 @@ module RAM32X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 4, abc_scc_break="D" *) +(* abc_box_id = 5, abc_scc_break="D" *) module RAM64X1D ( output DPO, SPO, input D, WCLK, WE, @@ -324,7 +325,7 @@ module RAM64X1D ( always @(posedge clk) if (WE) mem[a] <= D; endmodule -(* abc_box_id = 5, abc_scc_break="D" *) +(* abc_box_id = 6, abc_scc_break="D" *) module RAM128X1D ( output DPO, SPO, input D, WCLK, WE, |