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* Put attributes above portEddie Hung2019-08-232-27/+62
* Merge remote-tracking branch 'origin/master' into xaig_arrivalEddie Hung2019-08-231-5/+10
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| * Forgot oneEddie Hung2019-08-231-1/+2
| * Put abc_* attributes above portEddie Hung2019-08-231-7/+14
* | Use semicolonEddie Hung2019-08-211-1/+1
* | techmap before readEddie Hung2019-08-211-1/+1
* | Add abc_arrival to SRL*Eddie Hung2019-08-211-3/+5
* | OopsEddie Hung2019-08-201-1/+1
* | xilinx to use abc_map.v with -max_iter 1Eddie Hung2019-08-206-171/+26
* | Add reference to FD* timingEddie Hung2019-08-201-0/+2
* | Remove sequential extensionEddie Hung2019-08-206-359/+17
* | Remove SRL* delays from cells_sim.vEddie Hung2019-08-201-5/+3
* | LUTMUX -> LUTMUX6Eddie Hung2019-08-201-2/+2
* | Cleanup techmap in map_lutsEddie Hung2019-08-201-3/+5
* | Move `techmap abc_map.v` into map_lutsEddie Hung2019-08-201-1/+2
* | Remove delays from abc_map.vEddie Hung2019-08-201-5/+2
* | TypoEddie Hung2019-08-201-1/+1
* | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-204-16/+19
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| * Merge pull request #1209 from YosysHQ/eddie/synth_xilinxEddie Hung2019-08-204-16/+19
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| | * Merge remote-tracking branch 'origin/master' into eddie/synth_xilinxEddie Hung2019-08-203-6/+6
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| | * | Update Makefile tooEddie Hung2019-07-181-2/+2
| | * | Work in progress for renaming labels/options in synth_xilinxEddie Hung2019-07-183-14/+17
* | | | Wrap SRL{16,32} tooEddie Hung2019-08-203-7/+98
* | | | Wrap LUTRAMs in order to capture comb/seq behaviourEddie Hung2019-08-205-36/+200
* | | | Add LUTRAM delaysEddie Hung2019-08-201-3/+6
* | | | Remove mapping rulesEddie Hung2019-08-201-33/+0
* | | | Remove -icellsEddie Hung2019-08-201-2/+2
* | | | Use abc_{map,unmap,model}.vEddie Hung2019-08-207-110/+324
* | | | Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2019-08-201-2/+2
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| * | | Unify abc_carry_{in,out} into abc_carry and use port dir, as @mithroEddie Hung2019-08-191-2/+2
* | | | Add arrival times for SRL outputsEddie Hung2019-08-191-3/+5
* | | | Add BRAM arrival timesEddie Hung2019-08-191-8/+10
* | | | Add reference to source of Tclktoq timingEddie Hung2019-08-191-0/+2
* | | | Add 'abc_arrival' attribute for flop outputsEddie Hung2019-08-191-6/+6
* | | | Update box timingsEddie Hung2019-08-191-6/+9
* | | | Move from cell attr to module attrEddie Hung2019-08-191-12/+6
* | | | Use attributes instead of paramsEddie Hung2019-08-191-30/+12
* | | | Merge branch 'eddie/abc9_refactor' into xaig_dffEddie Hung2019-08-1612-25/+627
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| * | | Attach abc_scc_break, abc_carry_{in,out} attr to ports not modulesEddie Hung2019-08-161-8/+20
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| * | stoi -> atoiEddie Hung2019-08-071-1/+1
| * | RST -> RSTBRST for RAMB8BWEREddie Hung2019-07-291-3/+3
| * | xilinx: Fix missing cell name underscore in cells_map.vDavid Shah2019-07-251-2/+2
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| * Merge pull request #1182 from koriakin/xc6s-bramEddie Hung2019-07-119-8/+598
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| | * synth_xilinx: Initial Spartan 6 block RAM inference support.Marcin Koƛcielnicki2019-07-119-8/+598
| * | xilinx: Fix the default values for FDPE/FDSE INIT attributes to match ISE/Viv...Marcin Koƛcielnicki2019-07-112-6/+6
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* | Add Tsu offset to boxes, and commentsEddie Hung2019-07-111-6/+11
* | ABC doesn't like negative delays in flop boxes...Eddie Hung2019-07-111-6/+6
* | Fix FDCE_1 boxEddie Hung2019-07-111-1/+1
* | Revert "$pastQ should be first input"Eddie Hung2019-07-111-13/+13
* | Propagate INIT attrEddie Hung2019-07-111-5/+5