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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:39:11 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-20 12:39:11 -0700 |
| commit | be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68 (patch) | |
| tree | 793d391e5b20a0214d608c7dfe0cf894be143819 /techlibs/xilinx/cells_sim.v | |
| parent | c4d4c6db3f4bff22b2fa3a152c5c33d648af81f8 (diff) | |
| download | yosys-be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68.tar.gz yosys-be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68.tar.bz2 yosys-be9e4f1b674ef4fb3f02e99efcfda04ea27b2a68.zip | |
Use abc_{map,unmap,model}.v
Diffstat (limited to 'techlibs/xilinx/cells_sim.v')
| -rw-r--r-- | techlibs/xilinx/cells_sim.v | 8 |
1 files changed, 0 insertions, 8 deletions
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index dd5a76752..614fd8eef 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -169,14 +169,6 @@ module MUXF8(output O, input I0, I1, S); assign O = S ? I1 : I0; endmodule -`ifdef _ABC -(* abc_box_id = 3, lib_whitebox *) -module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); - assign O = S1 ? (S0 ? I3 : I2) - : (S0 ? I1 : I0); -endmodule -`endif - module XORCY(output O, input CI, LI); assign O = CI ^ LI; endmodule |