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* Remove now-redundant dff2dffs pass.Marcelina Kościelnicka2020-08-071-50/+0
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* peepopt: Remove now-redundant dffmux pattern.Marcelina Kościelnicka2020-08-072-143/+129
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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-078-34/+31
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* Add dffunmap pass.Marcelina Kościelnicka2020-07-311-0/+100
| | | | | To be used with backends that cannot deal with fancy FF types (like blif or smt).
* opt_expr: Remove -clkinv option, make it the default.Marcelina Kościelnicka2020-07-311-2/+1
| | | | | Adds -noclkinv option just in case the old behavior was actually useful to someone.
* synth_ice40: Use opt_dff.Marcelina Kościelnicka2020-07-301-1/+1
| | | | | | | | | The main part is converting ice40_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the mux patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* synth_xilinx: Use opt_dff.Marcelina Kościelnicka2020-07-301-9/+7
| | | | | | | | | The main part is converting xilinx_dsp to recognize the new FF types created in opt_dff instead of trying to recognize the patterns on its own. The fsm call has been moved upwards because the passes cannot deal with $dffe/$sdff*, and other optimizations don't help it much anyway.
* Add opt_dff pass.Marcelina Kościelnicka2020-07-3010-3/+914
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* opt_expr: Fix handling of $_XNOR_ cells with A = B.Marcelina Kościelnicka2020-07-291-0/+14
| | | | Fixes #2311.
* Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undefclairexen2020-07-281-0/+35
|\ | | | | equiv_induct: Fix up assumption for $equiv cells in -undef mode.
| * equiv_induct: Fix up assumption for $equiv cells in -undef mode.Marcelina Kościelnicka2020-07-271-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Before this fix, equiv_induct only assumed that one of the following is true: - defined value of A is equal to defined value of B - A is undefined This lets through valuations where A is defined, B is undefined, and the defined (meaningless) value of B happens to match the defined value of A. Instead, tighten this up to OR of the following: - defined value of A is equal to defined value of B, and B is not undefined - A is undefined
* | intel_alm: direct M10K instantiationDan Ravensloft2020-07-271-0/+6
| | | | | | | | This reverts commit a3a90f6377f251d3b6c5898eb1543f8832493bb8.
* | intel_alm: increase abc9 -WDan Ravensloft2020-07-261-6/+6
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* | Merge pull request #2299 from zachjs/arg-loopclairexen2020-07-262-0/+45
|\ \ | |/ |/| Avoid generating wires for function args which are constant
| * Avoid generating wires for function args which are constantZachary Snow2020-07-242-0/+45
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* | zinit: Refactor to use FfInitVals.Marcelina Kościelnicka2020-07-241-2/+2
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* | clk2fflogic: Support all FF types.Marcelina Kościelnicka2020-07-2419-124/+123
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* | satgen: Add support for dffe, sdff, sdffe, sdffce cells.Marcelina Kościelnicka2020-07-242-2/+21
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* Merge pull request #2285 from YosysHQ/mwk/techmap-cellnameclairexen2020-07-231-0/+41
|\ | | | | techmap: Add _TECHMAP_CELLNAME_ special parameter.
| * techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-0/+41
| | | | | | | | | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* | intel_alm: add additional ABC9 timingsDan Ravensloft2020-07-231-6/+4
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* Merge pull request #2238 from YosysHQ/mwk/dfflegalize-anlogicMiodrag Milanović2020-07-161-12/+14
|\ | | | | anlogic: Use dfflegalize.
| * anlogic: Use dfflegalize.Marcelina Kościelnicka2020-07-141-12/+14
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* | Merge pull request #2257 from antmicro/fix-conflictsclairexen2020-07-154-0/+49
|\ \ | | | | | | Restore #2203 and #2244 and fix parser conflicts
| * | Revert "Revert PRs #2203 and #2244."Kamil Rakoczy2020-07-104-0/+49
| | | | | | | | | | | | This reverts commit 9c120b89ace6c111aa4677616947d18d980b9c1a.
* | | Revert "intel_alm: direct M10K instantiation"Lofty2020-07-131-6/+0
| | | | | | | | | | | | This reverts commit 09ecb9b2cf3ab76841d30712bf70dafc6d47ef67.
* | | xilinx: Fix srl regression.Marcelina Kościelnicka2020-07-121-0/+41
|/ / | | | | | | | | | | | | Of standard yosys cells, xilinx_srl only works on $_DFF_?_ and $_DFFE_?P_, which get upgraded to $_SDFFE_?P?P_ by dfflegalize at the point where xilinx_srl is called for non-abc9. Fix this by running ff_map.v first, resulting in FDRE cells, which are handled correctly.
* | Revert PRs #2203 and #2244.whitequark2020-07-094-49/+0
| | | | | | | | | | | | | | | | This reverts commit 7e83a51fc96495c558a31fc3ca6c1a5ba4764f15. This reverts commit b422f2e4d0b8d5bfa97913d6b9dee488b59fc405. This reverts commit 7cb56f34b06de666935fbda315ce7c7bd45048b3. This reverts commit 6f9be939bd7653b0bdcae93a1033a086a4561b68. This reverts commit 76a34dc5f3a60c89efeaa3378ca0e2700a8aebd2.
* | dfflibmap: Refactor to use dfflegalize internally.Marcelina Kościelnicka2020-07-094-1/+136
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* | clkbufmap: improve input pad handling.Marcelina Kościelnicka2020-07-091-0/+79
| | | | | | | | | | | | - allow inserting only the input pad cell - do not insert the usual buffer if the input pad already acts as a buffer
* | Merge pull request #2244 from antmicro/logicclairexen2020-07-093-0/+21
|\ \ | | | | | | Add logic type support to parameters
| * | Add logic param and integer bad syntax testsKamil Rakoczy2020-07-063-0/+21
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | clk2fflogic: Consistently treat async control signals as negative hold.Marcelina Kościelnicka2020-07-097-31/+31
| | | | | | | | | | | | | | | | | | | | | This fixes some dfflegalize equivalence checks, and breaks others — and I strongly suspect the others are due to bad support for multiple async inputs in `proc` (in particular, lack of proper support for dlatchsr and sketchy circuits on dffsr control inputs).
* | | dfflegalize: Add special support for const-D latches.Marcelina Kościelnicka2020-07-091-0/+53
| | | | | | | | | | | | | | | | | | Those can be created by `opt_dff` when optimizing `$adff` with const clock, or with D == Q. Make dfflegalize do the opposite transform when such dlatches would be otherwise unimplementable.
* | | gowin: Use dfflegalize.Marcelina Kościelnicka2020-07-062-13/+8
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* | intel_alm: direct M10K instantiationDan Ravensloft2020-07-051-0/+6
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* | synth_gowin: ABC9 supportDan Ravensloft2020-07-051-1/+5
| | | | | | | | | | This adds ABC9 support for synth_gowin; drastically improving synthesis quality.
* | intel_alm: add Cyclone 10 GX testsDan Ravensloft2020-07-0511-2/+236
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* | opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.Marcelina Kościelnicka2020-07-051-0/+16
| | | | | | | | Fixes #2221.
* | intel_alm: DSP inferenceDan Ravensloft2020-07-051-0/+23
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* | synth_intel_alm: Use dfflegalize.Marcelina Kościelnicka2020-07-041-1/+1
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* | Improve MISTRAL_FF specify rulesDan Ravensloft2020-07-041-1/+2
| | | | | | | | Co-authored-by: Eddie Hung <eddie@fpgeh.com>
* | tests: update fsm.ys resource countEddie Hung2020-07-041-4/+4
|/ | | | | Suspect it is to do with map/set ordering in techmap; should be fixed by #1862?
* Merge pull request #2186 from YosysHQ/mwk/dfflegalizeclairexen2020-07-0217-0/+2957
|\ | | | | Add dfflegalize pass.
| * dfflegalize: Add tests.Marcelina Kościelnicka2020-07-0117-0/+2957
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* | Merge pull request #2203 from antmicro/fix-grammarclairexen2020-07-011-0/+28
|\ \ | | | | | | Signed and macro grammar update
| * | Add signed/unsigned testsKamil Rakoczy2020-06-261-0/+28
| | | | | | | | | | | | Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* | | Merge pull request #2179 from splhack/static-castclairexen2020-07-015-0/+80
|\ \ \ | | | | | | | | Support SystemVerilog Static Cast
| * | | static cast: add testsKazuki Sakamoto2020-06-195-0/+80
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* | | | Allow constant function calls in for loops and generate if and caseZachary Snow2020-06-292-0/+76
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