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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-03 00:22:44 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-14 05:02:50 +0200 |
| commit | 3050454d6e80ddb7603f7d5cc117b440a6bd8ab8 (patch) | |
| tree | 1ffb007dd3d321621d52de7099c71b9399d698fb /tests | |
| parent | 3d8d98d7093aa92f858a98d21a82cd453d8481dc (diff) | |
| download | yosys-3050454d6e80ddb7603f7d5cc117b440a6bd8ab8.tar.gz yosys-3050454d6e80ddb7603f7d5cc117b440a6bd8ab8.tar.bz2 yosys-3050454d6e80ddb7603f7d5cc117b440a6bd8ab8.zip | |
anlogic: Use dfflegalize.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/arch/anlogic/latches.ys | 26 |
1 files changed, 14 insertions, 12 deletions
diff --git a/tests/arch/anlogic/latches.ys b/tests/arch/anlogic/latches.ys index 8d66f77b3..34a3b14d0 100644 --- a/tests/arch/anlogic/latches.ys +++ b/tests/arch/anlogic/latches.ys @@ -3,31 +3,33 @@ design -save read hierarchy -top latchp proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchp # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-none t:AL_MAP_LUT3 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-count 1 t:AL_MAP_LUT1 +select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT1 %% t:* %D design -load read hierarchy -top latchn proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchn # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT3 -select -assert-none t:AL_MAP_LUT3 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-none t:AL_MAP_SEQ %% t:* %D design -load read hierarchy -top latchsr proc -# Can't run any sort of equivalence check because latches are blown to LUTs -synth_anlogic +equiv_opt -assert -multiclock -map +/anlogic/cells_sim.v synth_anlogic +design -load postopt cd latchsr # Constrain all select calls below inside the top module -select -assert-count 1 t:AL_MAP_LUT5 -select -assert-none t:AL_MAP_LUT5 %% t:* %D +select -assert-count 1 t:AL_MAP_SEQ +select -assert-count 2 t:AL_MAP_LUT3 +select -assert-none t:AL_MAP_SEQ t:AL_MAP_LUT3 %% t:* %D |