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authorclairexen <claire@symbioticeda.com>2020-07-28 12:56:22 +0200
committerGitHub <noreply@github.com>2020-07-28 12:56:22 +0200
commit66afed6f55be9c32eb2a1eef921633b302efa9c4 (patch)
tree3bd90b24e40dd45430bb2e67b99130c8c5fe11b5 /tests
parenta2fb84fd0c5f57b601b6a3c4cee0b409d74b5d21 (diff)
parenta1a0abf52afe397e11b63bfc67e82aaf7bf9f498 (diff)
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Merge pull request #2306 from YosysHQ/mwk/equiv_induct-undef
equiv_induct: Fix up assumption for $equiv cells in -undef mode.
Diffstat (limited to 'tests')
-rw-r--r--tests/various/equiv_opt_undef.ys35
1 files changed, 35 insertions, 0 deletions
diff --git a/tests/various/equiv_opt_undef.ys b/tests/various/equiv_opt_undef.ys
new file mode 100644
index 000000000..5d2c60d0a
--- /dev/null
+++ b/tests/various/equiv_opt_undef.ys
@@ -0,0 +1,35 @@
+read_ilang << EOT
+
+module \top
+ wire $a
+ wire $b
+ wire input 1 \D
+ wire input 2 \EN
+ wire output 3 \Q
+ cell $mux $x
+ parameter \WIDTH 1
+ connect \A \Q
+ connect \B \D
+ connect \S \EN
+ connect \Y $a
+ end
+ cell $ff $y
+ parameter \WIDTH 1
+ connect \D $a
+ connect \Q $b
+ end
+ cell $and $z
+ parameter \A_SIGNED 0
+ parameter \A_WIDTH 1
+ parameter \B_SIGNED 0
+ parameter \B_WIDTH 1
+ parameter \Y_WIDTH 1
+ connect \A $b
+ connect \B 1'x
+ connect \Y \Q
+ end
+end
+
+EOT
+
+equiv_opt -assert -undef ls