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| author | clairexen <claire@symbioticeda.com> | 2020-07-09 18:39:30 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-07-09 18:39:30 +0200 |
| commit | 802671b22edbedda593d4c256423975786c581a3 (patch) | |
| tree | 64e77efb358aefd438d4cf1ed87ab0852a8519e4 /tests | |
| parent | 03e28f7ab43116cd4f7fed0e37647637a4d8eda0 (diff) | |
| parent | b422f2e4d0b8d5bfa97913d6b9dee488b59fc405 (diff) | |
| download | yosys-802671b22edbedda593d4c256423975786c581a3.tar.gz yosys-802671b22edbedda593d4c256423975786c581a3.tar.bz2 yosys-802671b22edbedda593d4c256423975786c581a3.zip | |
Merge pull request #2244 from antmicro/logic
Add logic type support to parameters
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/various/integer_range_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/integer_real_bad_syntax.ys | 6 | ||||
| -rw-r--r-- | tests/various/logic_param_simple.ys | 9 |
3 files changed, 21 insertions, 0 deletions
diff --git a/tests/various/integer_range_bad_syntax.ys b/tests/various/integer_range_bad_syntax.ys new file mode 100644 index 000000000..4f427211f --- /dev/null +++ b/tests/various/integer_range_bad_syntax.ys @@ -0,0 +1,6 @@ +logger -expect error "syntax error, unexpected" 1 +read_verilog -sv <<EOT +module test_integer_range(); +parameter integer [31:0] a = 0; +endmodule +EOT diff --git a/tests/various/integer_real_bad_syntax.ys b/tests/various/integer_real_bad_syntax.ys new file mode 100644 index 000000000..942d8de77 --- /dev/null +++ b/tests/various/integer_real_bad_syntax.ys @@ -0,0 +1,6 @@ +logger -expect error "syntax error, unexpected TOK_REAL" 1 +read_verilog -sv <<EOT +module test_integer_real(); +parameter integer real a = 0; +endmodule +EOT diff --git a/tests/various/logic_param_simple.ys b/tests/various/logic_param_simple.ys new file mode 100644 index 000000000..968564080 --- /dev/null +++ b/tests/various/logic_param_simple.ys @@ -0,0 +1,9 @@ +read_verilog -sv <<EOT +module test_logic_param(); +parameter logic a = 0; +parameter logic [31:0] e = 0; +parameter logic signed b = 0; +parameter logic unsigned c = 0; +parameter logic unsigned [31:0] d = 0; +endmodule +EOT |