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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 00:55:38 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-05 06:31:58 +0200 |
| commit | 7afcb72c98620adaace7cc9622c4d577668f9426 (patch) | |
| tree | 762818adb15f5a4a1611d5f9ff1facbcd966bca9 /tests | |
| parent | b004f0901873962ba4a6fd3e12c7bc0cc1e04032 (diff) | |
| download | yosys-7afcb72c98620adaace7cc9622c4d577668f9426.tar.gz yosys-7afcb72c98620adaace7cc9622c4d577668f9426.tar.bz2 yosys-7afcb72c98620adaace7cc9622c4d577668f9426.zip | |
opt_expr: Fix crash on $mul optimization with more zeros removed than Y has.
Fixes #2221.
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/bug2221.ys | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/tests/opt/bug2221.ys b/tests/opt/bug2221.ys new file mode 100644 index 000000000..8ac380243 --- /dev/null +++ b/tests/opt/bug2221.ys @@ -0,0 +1,16 @@ +read_verilog <<EOT +module test ( + input [1:0] a, + input [1:0] b, + output [5:0] y +); + +wire [5:0] aa = {a, 4'h0}; +wire [5:0] bb = {b, 4'h0}; + +assign y = aa * bb; + +endmodule +EOT + +equiv_opt -assert opt_expr |