diff options
author | Zachary Snow <zach@zachjs.com> | 2020-06-26 19:52:36 -0700 |
---|---|---|
committer | Zachary Snow <zach@zachjs.com> | 2020-06-29 16:06:17 -0600 |
commit | 27cec16cda7d10e94931b25711358da2b382fdbf (patch) | |
tree | 0aa166b168110f903e8ac5f3f22d1e0b028ef14b /tests | |
parent | 4160acc0b19532d50435abbc66bd2f6aab9473b6 (diff) | |
download | yosys-27cec16cda7d10e94931b25711358da2b382fdbf.tar.gz yosys-27cec16cda7d10e94931b25711358da2b382fdbf.tar.bz2 yosys-27cec16cda7d10e94931b25711358da2b382fdbf.zip |
Allow constant function calls in for loops and generate if and case
Diffstat (limited to 'tests')
-rw-r--r-- | tests/various/const_func.v | 75 | ||||
-rw-r--r-- | tests/various/const_func.ys | 1 |
2 files changed, 76 insertions, 0 deletions
diff --git a/tests/various/const_func.v b/tests/various/const_func.v new file mode 100644 index 000000000..76cdc385d --- /dev/null +++ b/tests/various/const_func.v @@ -0,0 +1,75 @@ +module Example(outA, outB, outC, outD); + parameter OUTPUT = "FOO"; + output wire [23:0] outA; + output wire [23:0] outB; + output reg outC, outD; + function automatic [23:0] flip; + input [23:0] inp; + flip = ~inp; + endfunction + + generate + if (flip(OUTPUT) == flip("BAR")) + assign outA = OUTPUT; + else + assign outA = 0; + + case (flip(OUTPUT)) + flip("FOO"): assign outB = OUTPUT; + flip("BAR"): assign outB = 0; + flip("BAZ"): assign outB = "HI"; + endcase + + genvar i; + initial outC = 0; + for (i = 0; i != flip(flip(OUTPUT[15:8])); i = i + 1) + if (i + 1 == flip(flip("O"))) + initial outC = 1; + endgenerate + + integer j; + initial begin + outD = 1; + for (j = 0; j != flip(flip(OUTPUT[15:8])); j = j + 1) + if (j + 1 == flip(flip("O"))) + outD = 0; + end +endmodule + +module top(out); + wire [23:0] a1, a2, a3, a4; + wire [23:0] b1, b2, b3, b4; + wire c1, c2, c3, c4; + wire d1, d2, d3, d4; + Example e1(a1, b1, c1, d1); + Example #("FOO") e2(a2, b2, c2, d2); + Example #("BAR") e3(a3, b3, c3, d3); + Example #("BAZ") e4(a4, b4, c4, d4); + + output wire [24 * 8 - 1 + 4 :0] out; + assign out = { + a1, a2, a3, a4, + b1, b2, b3, b4, + c1, c2, c3, c4, + d1, d2, d3, d4}; + +// `define VERIFY +`ifdef VERIFY + assert property (a1 == 0); + assert property (a2 == 0); + assert property (a3 == "BAR"); + assert property (a4 == 0); + assert property (b1 == "FOO"); + assert property (b2 == "FOO"); + assert property (b3 == 0); + assert property (b4 == "HI"); + assert property (c1 == 1); + assert property (c2 == 1); + assert property (c3 == 0); + assert property (c4 == 0); + assert property (d1 == 0); + assert property (d2 == 0); + assert property (d3 == 1); + assert property (d4 == 1); +`endif +endmodule diff --git a/tests/various/const_func.ys b/tests/various/const_func.ys new file mode 100644 index 000000000..5e3c04105 --- /dev/null +++ b/tests/various/const_func.ys @@ -0,0 +1 @@ +read_verilog const_func.v |