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| * | ast: Fix handling of identifiers in the global scopeDavid Shah2020-04-161-0/+18
| |/ | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* / opt_expr: Fix X and CO outputs for $alu identity-mapping rules.Marcelina Kościelnicka2020-04-161-8/+66
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* Merge pull request #1933 from YosysHQ/eddie/zinit_moreEddie Hung2020-04-151-2/+96
|\ | | | | zinit: handle $__DFFS?E?_[NP][NP][01] too
| * tests: zinit for new typesEddie Hung2020-04-141-2/+96
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* | Merge pull request #1930 from YosysHQ/claire/fix1876Claire Wolf2020-04-151-0/+60
|\ \ | | | | | | Fix handling of ternary with constant condition
| * | tests: add testcases from #1876Eddie Hung2020-04-141-0/+60
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* | synth_intel_alm: alternative synthesis for Intel FPGAsDan Ravensloft2020-04-1510-0/+208
| | | | | | | | | | | | | | | | By operating at a layer of abstraction over the rather clumsy Intel primitives, we can avoid special hacks like `dffinit -highlow` in favour of simple techmapping. This also makes the primitives much easier to manipulate, and more descriptive (no more cyclonev_lcell_comb to mean anything from a LUT2 to a LUT6).
* | opt_expr: Add more $alu optimizations.Marcelina Kościelnicka2020-04-141-4/+52
|/ | | | | | | | | | | Detect the places in the $alu where the carry bit is constant (due to const A[i] == B[i] ^ BI) and split it into smaller $alu at these points. Also, make the existing const-carry detection for low bits more generic (now handles cases where both BI and CI are constant, but not equal to one another). Fixes #1912.
* dffinit: Avoid setting init parameter to zero-length value.Marcelina Kościelnicka2020-04-141-0/+25
| | | | Fixes #1704.
* Merge pull request #1879 from jjj11x/jjj11x/package_declwhitequark2020-04-141-3/+8
|\ | | | | support using previously declared types/localparams/parameters in package
| * support using previously declared types/localparams/params in packageJeff Wang2020-04-071-3/+8
| | | | | | | | | | | | | | (parameters in systemverilog packages can't actually be overridden, so allowing parameters in addition to localparams doesn't actually add any new functionality, but it's useful to be able to use the parameter keyword also)
* | zinit: resolve one more comment by @mwkmwkmwkEddie Hung2020-04-131-1/+8
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* | zinit: fix review comments from @mwkmwkmwkEddie Hung2020-04-131-4/+31
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* | tests: zinit on $adffEddie Hung2020-04-131-19/+18
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* | Add testcase for $_DFF_[NP][NP][01]_Eddie Hung2020-04-131-0/+24
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* | opt_expr: Optimize multiplications with low 0 bits in operands.Marcelina Kościelnicka2020-04-131-0/+28
| | | | | | | | Fixes #1500.
* | Add .gitignore to tests/select/Xiretza2020-04-121-0/+1
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* | Merge pull request #1603 from whitequark/ice40-ram_stylewhitequark2020-04-105-35/+551
|\ \ | | | | | | ice40/ecp5: add support for both 1364.1 and Synplify/LSE RAM/ROM attributes
| * | ecp5: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-16/+62
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| * | ice40: do not map FFRAM if explicitly requested otherwise.whitequark2020-04-031-8/+28
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| * | ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-5/+305
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | ice40: match memory inference attribute values case insensitive.whitequark2020-02-061-0/+6
| | | | | | | | | | | | LSE/Synplify use case insensitive matching.
| * | ice40: add support for both 1364.1 and LSE RAM/ROM attributes.whitequark2020-02-063-20/+179
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit tries to carefully follow the documented behavior of LSE and Synplify. It will use `syn_ramstyle` attribute if there are any write ports, and `syn_romstyle` attribute otherwise. * LSE supports both `syn_ramstyle` and `syn_romstyle`. * Synplify only supports `syn_ramstyle`, with same values as LSE. * Synplify also supports `syn_rw_conflict_logic`, which is not documented as supported for LSE. Limitations of the Yosys implementation: * LSE/Synplify appear to interpret attribute values insensitive to case. There is currently no way to do this in Yosys (attrmap can only change case of attribute names). * LSE/Synplify support `syn_ramstyle="block_ram,no_rw_check"` syntax to turn off insertion of transparency logic. There is currently no way to support multiple valued attributes in memory_bram. It is also not clear if that is a good idea, since it can cause sim/synth mismatches. * LSE/Synplify/1364.1 support block ROM inference from full case statements. Yosys does not currently perform this transformation. * LSE/Synplify propagate `syn_ramstyle`/`syn_romstyle` attributes from the module to the inner memories. There is currently no way to do this in Yosys (attrmvcp only works on cells and wires).
| * | ice40: remove impossible test.whitequark2020-02-061-15/+0
| | | | | | | | | | | | | | | | | | iCE40 does not have LUTRAM. This was erroneously added in commit caab66111e2b5052bd26c8fd64b1324e7e4a4106, and tested for BRAM, essentially a duplicate of the "dpram.ys" test.
* | | tests: add a quick plugin testEddie Hung2020-04-093-0/+22
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* | Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-0/+52
|\ \ | | | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * | +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
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| * | Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-1/+1
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| * | techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+24
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* | | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+9
|/ / | | | | | | Fixes #1841.
* | Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-013-7/+55
|\ \ | | | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
| * | opt_expr: add failing $xnor testEddie Hung2020-03-201-1/+13
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| * | Simplify breaking tests/arch/*/fsm.ys testsEddie Hung2020-03-202-7/+3
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| * | opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ testsEddie Hung2020-03-191-0/+40
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* | | Merge pull request #1789 from YosysHQ/eddie/opt_expr_aluEddie Hung2020-04-011-0/+63
|\ \ \ | | | | | | | | opt_expr: improve performance on $alu and $sub
| * | | opt_expr: add $alu testsEddie Hung2020-03-191-0/+63
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* | | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-0/+12
|\ \ \ | | | | | | | | ast: simplify to fully populate dynamic slicing case transformation
| * | | Add dynamic slicing Verilog testcaseEddie Hung2020-03-311-0/+12
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* | | Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedupEddie Hung2020-03-312-0/+92
|\ \ \ | | | | | | | | opt_merge: speedup
| * | | opt_merge: speedupEddie Hung2020-03-162-0/+92
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* | | Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-301-0/+7
|\ \ \ | | | | | | | | Support module/package/interface/block scope for typedef names.
| * | | Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-0/+7
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* | | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | | | Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-261-0/+18
|\ \ \ \ | | | | | | | | | | techmap: Fix cell names with _TECHMAP_REPLACE_.*
| * | | | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-0/+18
| | | | | | | | | | | | | | | | | | | | Fixes #1804.
* | | | | Merge pull request #1763 from boqwxp/issue1762N. Engelhardt2020-03-235-0/+19
|\ \ \ \ \ | |_|/ / / |/| | | | Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
| * | | | Do not warn on empty selection with prefixed `arg_memb`.Alberto Gonzalez2020-03-231-0/+5
| | | | | | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | | Suppress warnings for empty `select` arguments when `-count` or `-assert-*` ↵Alberto Gonzalez2020-03-231-0/+2
| | | | | | | | | | | | | | | | | | | | options are set.
| * | | | Add tests for `select` command warnings.Alberto Gonzalez2020-03-233-0/+12
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* | | | | Merge pull request #1803 from Grazfather/typedefN. Engelhardt2020-03-237-25/+26
|\ \ \ \ \ | |_|/ / / |/| | | | Support standard typedef grammar (Fixed)
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