iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	abc9: respect (* keep *) on cells	Eddie Hung	2020-01-13	1	-0/+15
*	write_xaiger: add support and test for (* keep *) on wires	Eddie Hung	2020-01-13	1	-0/+13
*	Merge pull request #1620 from YosysHQ/eddie/abc9_scratchpad	Eddie Hung	2020-01-13	1	-0/+40
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\| *	Merge remote-tracking branch 'origin/master' into eddie/abc9_scratchpad	Eddie Hung	2020-01-11	1	-0/+25
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\| * \|	Add abc9 sanity test	Eddie Hung	2020-01-09	1	-0/+40
* \| \|	Add #1626 testcase	Eddie Hung	2020-01-12	1	-0/+217
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* \|	Merge remote-tracking branch 'origin/master' into eddie/abc9_mfs	Eddie Hung	2020-01-07	9	-4/+196
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\| *	Add testcases	Eddie Hung	2020-01-07	2	-0/+17
\| *	tests/aiger: write Yosys output	Eddie Hung	2020-01-07	1	-2/+2
\| *	Combine tests to check multiple clock domains	Eddie Hung	2020-01-02	1	-33/+10
\| *	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2020-01-02	10	-11/+31
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\| * \|	Add some abc9 dff tests	Eddie Hung	2019-12-31	1	-0/+55
\| * \|	Add -D DFF_MODE to abc9_map test	Eddie Hung	2019-12-30	1	-4/+4
\| * \|	Remove submod changes	Eddie Hung	2019-12-30	1	-102/+0
\| * \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-30	25	-57/+247
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\| * \ \	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-20	2	-3/+35
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\| * \ \ \	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-19	21	-66/+755
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\| * \| \| \| \|	abc9 needs a clean afterwards	Eddie Hung	2019-12-16	1	-2/+4
\| * \| \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-12	3	-23/+136
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\| * \ \ \ \ \	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-12-06	6	-8/+412
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\| * \| \| \| \| \| \|	abc9_map.v to transform INIT=1 to INIT=0	Eddie Hung	2019-12-04	1	-0/+91
\| * \| \| \| \| \| \|	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	Eddie Hung	2019-11-27	1	-0/+31
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\| \| * \| \| \| \| \| \|	Add multiple driver testcase	Eddie Hung	2019-11-27	1	-0/+31
\| * \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-11-27	2	-0/+82
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\| * \ \ \ \ \ \ \ \	Merge remote-tracking branch 'origin/eddie/write_xaiger_improve' into xaig_dff	Eddie Hung	2019-11-27	1	-9/+0
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\| * \ \ \ \ \ \ \ \ \	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	Eddie Hung	2019-11-27	1	-2/+23
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\| \| * \| \| \| \| \| \| \| \|	Revert "submod to bitty rather bussy, for bussy wires used as input and output"	Eddie Hung	2019-11-27	1	-2/+5
\| \| * \| \| \| \| \| \| \| \|	Fix wire width	Eddie Hung	2019-11-26	1	-2/+2
\| \| * \| \| \| \| \| \| \| \|	Add testcase where \init is copied	Eddie Hung	2019-11-25	1	-0/+18
\| * \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-11-25	5	-13/+24
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\| * \ \ \ \ \ \ \ \ \ \	Merge branch 'xaig_dff' of github.com:YosysHQ/yosys into xaig_dff	Eddie Hung	2019-11-23	3	-11/+11
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\| \| * \| \| \| \| \| \| \| \| \| \|	Another sloppy mistake!	Eddie Hung	2019-11-21	1	-1/+1
\| \| * \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/xaig_dff' into eddie/xaig_dff_adff	Eddie Hung	2019-11-21	3	-4/+9
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\| \| * \| \| \| \| \| \| \| \| \| \| \|	async2sync -> clk2fflogic	Eddie Hung	2019-11-21	1	-1/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	Eddie Hung	2019-11-22	1	-3/+0
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\| \| * \| \| \| \| \| \| \| \| \| \| \|	Remove redundant flatten	Eddie Hung	2019-11-22	1	-2/+0
\| \| * \| \| \| \| \| \| \| \| \| \| \|	Stray dump	Eddie Hung	2019-11-22	1	-1/+0
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	Eddie Hung	2019-11-22	1	-0/+28
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\| \| * \| \| \| \| \| \| \| \| \| \| \|	Add another test with constant driver	Eddie Hung	2019-11-22	1	-0/+28
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Add testcase for signal used as part input part output	Eddie Hung	2019-11-22	1	-0/+5
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge remote-tracking branch 'origin/eddie/submod_po' into xaig_dff	Eddie Hung	2019-11-22	1	-0/+25
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\| \| * \| \| \| \| \| \| \| \| \| \| \|	Cleanup spacing	Eddie Hung	2019-11-22	1	-2/+1
\| \| * \| \| \| \| \| \| \| \| \| \| \|	Add testcase	Eddie Hung	2019-11-22	1	-0/+26
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'eddie/clkpart' into xaig_dff	Eddie Hung	2019-11-22	2	-1/+63
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\| * \| \| \| \| \| \| \| \| \| \| \| \|	Missing endmodule	Eddie Hung	2019-11-22	1	-0/+1
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Merge branch 'eddie/xaig_dff_adff' into xaig_dff	Eddie Hung	2019-11-21	3	-3/+37
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\| \| * \| \| \| \| \| \| \| \| \| \| \|	Add a equiv test too	Eddie Hung	2019-11-19	2	-0/+23
\| \| * \| \| \| \| \| \| \| \| \| \| \|	Add two tests	Eddie Hung	2019-11-19	1	-0/+12
\| * \| \| \| \| \| \| \| \| \| \| \| \|	Add test	Eddie Hung	2019-11-21	1	-1/+6
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\| * \| \| \| \| \| \| \| \| \| \| \|	Add multi clock test	Eddie Hung	2019-11-20	1	-0/+5
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