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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 19:21:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-01-13 19:21:11 -0800 |
| commit | a6d4ea74634826741f09793c36d596f2fa239f62 (patch) | |
| tree | 37e4bdc7f77b77c60d69516f9aa150c2c4c0579d /tests | |
| parent | 9ec948f3965eef214bee3af778b67fdd6ee86929 (diff) | |
| download | yosys-a6d4ea74634826741f09793c36d596f2fa239f62.tar.gz yosys-a6d4ea74634826741f09793c36d596f2fa239f62.tar.bz2 yosys-a6d4ea74634826741f09793c36d596f2fa239f62.zip | |
abc9: respect (* keep *) on cells
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/abc9.ys | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 46b6f08d2..d5a63e1cb 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -51,3 +51,18 @@ simplemap equiv_opt -assert abc9 -lut 4 design -load postopt select -assert-count 2 t:$lut + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +wire w; +(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b)); +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 1 t:$lut +select -assert-count 1 t:$_AND_ |