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Merge pull request #1930 from YosysHQ/claire/fix1876
Claire Wolf
2020-04-15
1
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+60
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tests: add testcases from #1876
Eddie Hung
2020-04-14
1
-0
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+60
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synth_intel_alm: alternative synthesis for Intel FPGAs
Dan Ravensloft
2020-04-15
10
-0
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+208
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opt_expr: Add more $alu optimizations.
Marcelina Kościelnicka
2020-04-14
1
-4
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+52
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dffinit: Avoid setting init parameter to zero-length value.
Marcelina Kościelnicka
2020-04-14
1
-0
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+25
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Merge pull request #1879 from jjj11x/jjj11x/package_decl
whitequark
2020-04-14
1
-3
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+8
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support using previously declared types/localparams/params in package
Jeff Wang
2020-04-07
1
-3
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+8
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zinit: resolve one more comment by @mwkmwkmwk
Eddie Hung
2020-04-13
1
-1
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+8
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zinit: fix review comments from @mwkmwkmwk
Eddie Hung
2020-04-13
1
-4
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+31
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tests: zinit on $adff
Eddie Hung
2020-04-13
1
-19
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+18
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Add testcase for $_DFF_[NP][NP][01]_
Eddie Hung
2020-04-13
1
-0
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+24
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opt_expr: Optimize multiplications with low 0 bits in operands.
Marcelina Kościelnicka
2020-04-13
1
-0
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+28
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Add .gitignore to tests/select/
Xiretza
2020-04-12
1
-0
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+1
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Merge pull request #1603 from whitequark/ice40-ram_style
whitequark
2020-04-10
5
-35
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+551
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ecp5: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-16
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+62
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ice40: do not map FFRAM if explicitly requested otherwise.
whitequark
2020-04-03
1
-8
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+28
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ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
3
-5
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+305
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ice40: match memory inference attribute values case insensitive.
whitequark
2020-02-06
1
-0
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+6
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ice40: add support for both 1364.1 and LSE RAM/ROM attributes.
whitequark
2020-02-06
3
-20
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+179
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ice40: remove impossible test.
whitequark
2020-02-06
1
-15
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+0
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tests: add a quick plugin test
Eddie Hung
2020-04-09
3
-0
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+22
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Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
Eddie Hung
2020-04-03
1
-0
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+52
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+/cmp2lcu.v to work efficiently for fully/partially constant inputs
Eddie Hung
2020-04-03
1
-3
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+31
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Refactor +/cmp2lcu.v into recursive techmap
Eddie Hung
2020-04-03
1
-1
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+1
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techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
Eddie Hung
2020-04-03
1
-0
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+24
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iopadmap: Fix z assignment to inout port
Marcin Kościelnicki
2020-04-02
1
-1
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+9
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Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
Eddie Hung
2020-04-01
3
-7
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+55
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opt_expr: add failing $xnor test
Eddie Hung
2020-03-20
1
-1
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+13
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Simplify breaking tests/arch/*/fsm.ys tests
Eddie Hung
2020-03-20
2
-7
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+3
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opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests
Eddie Hung
2020-03-19
1
-0
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+40
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Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
Eddie Hung
2020-04-01
1
-0
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+63
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opt_expr: add $alu tests
Eddie Hung
2020-03-19
1
-0
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+63
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Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
Claire Wolf
2020-04-01
1
-0
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+12
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Add dynamic slicing Verilog testcase
Eddie Hung
2020-03-31
1
-0
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+12
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Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup
Eddie Hung
2020-03-31
2
-0
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+92
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opt_merge: speedup
Eddie Hung
2020-03-16
2
-0
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+92
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Merge pull request #1811 from PeterCrozier/typedef_scope
N. Engelhardt
2020-03-30
1
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+7
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Support module/package/interface/block scope for typedef names.
Peter Crozier
2020-03-23
1
-0
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+7
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Add support for SystemVerilog-style `define to Verilog frontend
Rupert Swarbrick
2020-03-27
4
-0
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+50
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Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix
Claire Wolf
2020-03-26
1
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+18
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techmap: Fix cell names with _TECHMAP_REPLACE_.*
Marcin Kościelnicki
2020-03-23
1
-0
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+18
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Merge pull request #1763 from boqwxp/issue1762
N. Engelhardt
2020-03-23
5
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+19
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Do not warn on empty selection with prefixed `arg_memb`.
Alberto Gonzalez
2020-03-23
1
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+5
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Suppress warnings for empty `select` arguments when `-count` or `-assert-*` o...
Alberto Gonzalez
2020-03-23
1
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+2
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Add tests for `select` command warnings.
Alberto Gonzalez
2020-03-23
3
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+12
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Merge pull request #1803 from Grazfather/typedef
N. Engelhardt
2020-03-23
7
-25
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+26
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Revert typedef tests to standard grammar.
Peter
2020-03-22
7
-25
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+26
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Add test for abc9+mince issue
David Shah
2020-03-20
1
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+17
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fsm_extract: Initialize celltypes with full design.
Marcin Kościelnicki
2020-03-19
1
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+33
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Merge pull request #1774 from boqwxp/exec
N. Engelhardt
2020-03-19
1
-0
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+6
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