iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	tests: remove write_ilang	Eddie Hung	2020-04-20	2	-3/+0
*	abc9: add testcase reduced from #1970	Eddie Hung	2020-04-20	1	-0/+19
*	tests: add select -unset tests	Eddie Hung	2020-04-16	2	-0/+20
*	tests: add design -delete tests	Eddie Hung	2020-04-16	2	-0/+18
*	Merge pull request #1943 from YosysHQ/dave/fix-1919	David Shah	2020-04-16	1	-0/+18
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\| *	ast: Fix handling of identifiers in the global scope	David Shah	2020-04-16	1	-0/+18
* \|	opt_expr: Fix X and CO outputs for $alu identity-mapping rules.	Marcelina Kościelnicka	2020-04-16	1	-8/+66
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*	Merge pull request #1933 from YosysHQ/eddie/zinit_more	Eddie Hung	2020-04-15	1	-2/+96
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\| *	tests: zinit for new types	Eddie Hung	2020-04-14	1	-2/+96
* \|	Merge pull request #1930 from YosysHQ/claire/fix1876	Claire Wolf	2020-04-15	1	-0/+60
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\| * \|	tests: add testcases from #1876	Eddie Hung	2020-04-14	1	-0/+60
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* \|	synth_intel_alm: alternative synthesis for Intel FPGAs	Dan Ravensloft	2020-04-15	10	-0/+208
* \|	opt_expr: Add more $alu optimizations.	Marcelina Kościelnicka	2020-04-14	1	-4/+52
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*	dffinit: Avoid setting init parameter to zero-length value.	Marcelina Kościelnicka	2020-04-14	1	-0/+25
*	Merge pull request #1879 from jjj11x/jjj11x/package_decl	whitequark	2020-04-14	1	-3/+8
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\| *	support using previously declared types/localparams/params in package	Jeff Wang	2020-04-07	1	-3/+8
* \|	zinit: resolve one more comment by @mwkmwkmwk	Eddie Hung	2020-04-13	1	-1/+8
* \|	zinit: fix review comments from @mwkmwkmwk	Eddie Hung	2020-04-13	1	-4/+31
* \|	tests: zinit on $adff	Eddie Hung	2020-04-13	1	-19/+18
* \|	Add testcase for $_DFF_[NP][NP][01]_	Eddie Hung	2020-04-13	1	-0/+24
* \|	opt_expr: Optimize multiplications with low 0 bits in operands.	Marcelina Kościelnicka	2020-04-13	1	-0/+28
* \|	Add .gitignore to tests/select/	Xiretza	2020-04-12	1	-0/+1
* \|	Merge pull request #1603 from whitequark/ice40-ram_style	whitequark	2020-04-10	5	-35/+551
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\| * \|	ecp5: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-16/+62
\| * \|	ice40: do not map FFRAM if explicitly requested otherwise.	whitequark	2020-04-03	1	-8/+28
\| * \|	ecp5: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	3	-5/+305
\| * \|	ice40: match memory inference attribute values case insensitive.	whitequark	2020-02-06	1	-0/+6
\| * \|	ice40: add support for both 1364.1 and LSE RAM/ROM attributes.	whitequark	2020-02-06	3	-20/+179
\| * \|	ice40: remove impossible test.	whitequark	2020-02-06	1	-15/+0
* \| \|	tests: add a quick plugin test	Eddie Hung	2020-04-09	3	-0/+22
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* \|	Merge pull request #1648 from YosysHQ/eddie/cmp2lcu	Eddie Hung	2020-04-03	1	-0/+52
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\| * \|	+/cmp2lcu.v to work efficiently for fully/partially constant inputs	Eddie Hung	2020-04-03	1	-3/+31
\| * \|	Refactor +/cmp2lcu.v into recursive techmap	Eddie Hung	2020-04-03	1	-1/+1
\| * \|	techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu	Eddie Hung	2020-04-03	1	-0/+24
* \| \|	iopadmap: Fix z assignment to inout port	Marcin Kościelnicki	2020-04-02	1	-1/+9
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* \|	Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor	Eddie Hung	2020-04-01	3	-7/+55
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\| * \|	opt_expr: add failing $xnor test	Eddie Hung	2020-03-20	1	-1/+13
\| * \|	Simplify breaking tests/arch/*/fsm.ys tests	Eddie Hung	2020-03-20	2	-7/+3
\| * \|	opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ tests	Eddie Hung	2020-03-19	1	-0/+40
* \| \|	Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu	Eddie Hung	2020-04-01	1	-0/+63
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\| * \| \|	opt_expr: add $alu tests	Eddie Hung	2020-03-19	1	-0/+63
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* \| \|	Merge pull request #1848 from YosysHQ/eddie/fix_dynslice	Claire Wolf	2020-04-01	1	-0/+12
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\| * \| \|	Add dynamic slicing Verilog testcase	Eddie Hung	2020-03-31	1	-0/+12
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* \| \|	Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedup	Eddie Hung	2020-03-31	2	-0/+92
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\| * \| \|	opt_merge: speedup	Eddie Hung	2020-03-16	2	-0/+92
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* \| \|	Merge pull request #1811 from PeterCrozier/typedef_scope	N. Engelhardt	2020-03-30	1	-0/+7
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\| * \| \|	Support module/package/interface/block scope for typedef names.	Peter Crozier	2020-03-23	1	-0/+7
* \| \| \|	Add support for SystemVerilog-style `define to Verilog frontend	Rupert Swarbrick	2020-03-27	4	-0/+50
* \| \| \|	Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fix	Claire Wolf	2020-03-26	1	-0/+18
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\| * \| \| \|	techmap: Fix cell names with _TECHMAP_REPLACE_.*	Marcin Kościelnicki	2020-03-23	1	-0/+18